參數(shù)資料
型號(hào): IDT72V73263BB
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 35/36頁(yè)
文件大?。?/td> 0K
描述: IC DGTL SW 16384X16384 208-BGA
標(biāo)準(zhǔn)包裝: 12
系列: 72V
類型: 多路復(fù)用器
電路: 8 x 1:1
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 208-BGA
供應(yīng)商設(shè)備封裝: 208-PBGA(17x17)
包裝: 托盤
其它名稱: 72V73263BB
8
INDUSTRIAL TEMPERATURERANGE
IDT72V73263 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
TABLE 3 CONTROL REGISTER (CR) BITS
Reset Value:
0000H
15
14
13
12
11
10
987654
32
1
0
BIT
NAME
DESCRIPTION
15
SRS
A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.
(SoftwareReset)
14
BYP
WhentheBypassbitis1,allRXstreamswillbe"shorted"toTX—ineffectbypassingallinternalcircuitryoftheTSI. Thiseffectively
(RX/TXBypass)
setstheTSItoa1-to-1switchmodewithalmostonlyafewnanosecondsofdelay. Azerocanbewrittentoallownormaloperation.
TheintentionofthismodeistominimizethedelayfromtheRXinputtotheTXoutput makingtheTSI"invisible". Anyoffsetvalues
in the FOR register will be required.
13
OEPOL
When1,aoneonOEIpindenotesanactivestateontheoutputdatastream;zeroonOEIpindenotesHigh-Impedancestate. When
(OutputEnablePolarity)
0, a one denotes High-Impedance and a zero denotes an active state. OEI mode is entered on a per-group basis in the DRSR.
12
AOE
When1,alloutputstreampins(TXn)becomeOEItoallowforatwo-chipsolutionforalargerswitchingmatrixwithOEIpins. When
(AllOutputEnable)
in AOE the DRS must be set to the corresponding data rate of the other device.
11
PRST
When HIGH, the PRBS transmitter output will be initialized.
(PRBS Reset)
10
CBER
A low to high transititon of this bit clears the BER register (BERR).
(Clear Bit Error Rate)
9
SBER
A low to high transition in this bit starts the bit error rate test. The bit error test results is kept in the BER register (BERR).
(StartBitErrorRate)
8
FBP
When 1, this bit overrides the BPSA and BPEA registers and programs the full Connection Memory space. When 0, the BPSA
(FullBlockProgramming)
and BPEAdetermine the Connection Memory space to be programmed.
7-5
BPD2-0
ThesebitscarrythevaluetobeloadedintotheConnectionMemoryblockwhenevertheConnectionMemoryblockprogramming
(BlockProgrammingData) features is activated. After the BPE bit is set to 1 from 0, the contents of the bits BPD1-0 are loaded into bit 1 and 0 (MOD2-0) of
the Connection Memory HIGH.
4
BPE
AzerotoonetransitionofthisbitenablestheConnectionMemoryblockprogrammingfeaturedelimitedbytheBPSAandBPEA
(Begin Block
registersaswellasforafullblockprogram. OncetheBPEbitissetHIGH,thedevicewillprogramtheConnectionMemoryblock
ProgrammingEnable)
asfastasthaniftheusermanuallyprogrammedeachConnectionMemorylocationthroughthemicroprocessor. Aftertheprogramming
function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE bit can be
setto0toabortblockprogramming.
3
RCML
When RCML =1, all bits 14-0 in Connection Memory LOW will be reset to zero during block programming; when RCML = 0, bits
(ResetConnection
14-0inConnectionMemoryLOWwillretaintheiroriginalvaluesduringblockprogramming.
Memory LOW in Block
Programming)
2
OSB
When ODE = 0 and OSB = 0, the output drivers of transmit serial streams are in High-Impedance mode. When either ODE = 1
(OutputStandby)
or OSB = 1, the output serial stream drivers function normally.
1-0
MS1-0
These two bits decide which memory to be accessed via microprocessor port.
(Memory Select)
00 -- Connection Memory LOW
01 -- Connection Memory HIGH
10 -- Data Memory
11 -- Reserved
SRS
BYP
OEPOL
AOE
PRST
CBER
SBER
FBP
BPD2
BPD1
BPD0
BPE
RCML
OSB
MS1
MS0
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