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參數(shù)資料
| 型號： | IDT72V73250BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 8192X8192 144-BGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | 72V |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 16:16 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應(yīng)商設(shè)備封裝： | 144-PBGA（13x13） |
| 包裝： | 托盤 |
| 其它名稱： | 72V73250BB |
4
INDUSTRIAL TEMPERATURERANGE
IDT72V73250 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
PIN DESCRIPTION
SYMBOL
NAME
I/O
DESCRIPTION
A0-14
Address 0 to 14
I
These address lines access all internal memories.
C32i
Clock
I
Serial clock for shifting data in/out on the serial data stream. This input accepts a 32.768 MHz clock.
CS
Chip Select
I
This active LOW input is used by a microprocessor to activate the microprocessor port of IDT72V73250.
D0-15
Data Bus 0-15
I/O
These pins are the data bits of the microprocessor port.
DS
Data Strobe
I
This active LOW input works in conjunction with
CS to enable the read and write operations and sets the
data bus lines (D0-D15).
DTA
Data Transfer
O
Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes
Acknowledgment
high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required
to hold a HIGH level when the pin is in high-impedance.
FE
Frame Evaluation
I
This input can be used to measure delay in the data path by comparing the frame pulse, F32i, with this input.
F32i
Frame Pulse
I
This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUSand GCI specifications.
GND
Ground
Ground Rail
ODE
Output Drive Enable
I
This is the output enable control for the TX serial outputs. When the ODE input is LOW and the Output Stand
By bit of the Control Register is LOW, all TX outputs are in a high-impedance state. If this input is HIGH, the TX
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per-channel control bits in the Connection Memory.
RESET
Device Reset
I
This input puts the IDT72V73250 into a reset state that clears the device internal counters, registers and
brings TX0-15 and D0-D15 into a high-impedance state. The
RESET pin must be held LOW for a minimum
of 20ns to properly reset the device.
R/
W
Read/Write
I
This input controls the direction of the data bus lines (D0-D15) during a microprocessor access.
RX0-15
DataStream
I
Serial data input stream. These streams have a data rate of 32.768 Mb/s.
Input 0 to 15
TCK
Test Clock
I
Provides the clock to the JTAG test logic.
TDI
Test Serial Data In
I
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
TDO
Test Serial Data Out
O
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.
TMS
Test Mode Select
I
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.
TRST
TestReset
I
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
to ensure that the IDT72V73250 is in the normal functional mode.
TX0-7
TX Output 0 to 7
O
Serial data output stream. These streams have a data rate of 32.768 Mb/s.
(Three-StateOutputs)
TX8-15/
TX Output 8 to 15/
O
When all 16 output streams are selected via Control Register, these pins are the output streams TX8 to TX15
OEI0-7
Output Enable
and operate at 32.768Mb/s. When output enable function is selected, these pins reflect the active or high-
Indication0-7
impedance status for the corresponding output stream Output Enable Indication 0-7.
(Three-StateOutputs)
VCC
+3.3 Volt Power Supply.
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