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參數(shù)資料
| 型號： | IDT72V71650BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL SW 8192X8192 144-BGA |
| 標準包裝： | 10 |
| 系列： | 72V |
| 類型： | 多路復用器 |
| 電路： | 1 x 32:32 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應(yīng)商設(shè)備封裝： | 144-PBGA（13x13） |
| 包裝： | 托盤 |
| 其它名稱： | 72V71650BB |
6
INDUSTRIAL TEMPERATURERANGE
IDT72V71650 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
DELAY THROUGH THE IDT72V71650
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
ties on a per-channel basis. For voice applications, variable throughput delay
isbestasitensuresminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
information is maintained through the switch.
Thedelaythroughthedevicevariesaccordingtothetypeofthroughputdelay
selected in the MOD bits of the Connection Memory.
VARIABLE DELAY MODE (MOD1-0 = 0-0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V71650 is three time-slots. If the input
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
be output in the following frame (channel n, frame p+1). The same is true if the
input channel n is switched to output channel n+1 or n+2. If the input channel
n is switched to output channel n+3, n+4,..., the new output data will appear in
the same frame. Table 2 shows the possible delays for the IDT72V71650 in
Variable Delay mode.
CONSTANT DELAY MODE (MOD1-0 = 0-1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
theIDT72V71650,theminimumthroughputdelayachievableinConstantDelay
mode will be one frame plus one channel. See Table 1.
MICROPROCESSOR INTERFACE
The IDT72V71650’s microprocessor interface looks like a standard RAM
interface to improve integration into a system. With a 15-bit address bus and a
16-bitdatabus,readsandwritesaremappeddirectlyintoDataandConnection
Memories and require only one clock cycle to access. By allowing the internal
memoriestoberandomlyaccessedinonecycle,thecontrollingmicroprocessor
has more time to manage other peripheral devices and can more easily and
quickly gather information and setup the switch paths. Table 4 shows the
mapping of the addresses into internal memory blocks.
MEMORY MAPPING
Theaddressbusonthemicroprocessorinterfaceselectstheinternalregisters
and memories of the IDT72V71650.
Thetwomostsignificantbitsoftheaddressselectbetweentheregisters,Data
Memory,andConnectionMemory.IfA14andA13areHIGH,A12-A0areused
toaddresstheDataMemory.IfA14isHIGHandA13 isLOW,A12-A0areused
to address Connection Memory. If A14 is LOW and A13 is HIGH A12-A0 are
usedtoselecttheControlRegister,FrameAlignmentRegister,andFrameOffset
Registers. See Table 4 for mappings.
AsexplainedintheSerialDataInterfaceTimingandSwitchingConfigurations
sections, after system power-up, the Control Register should be programmed
immediatelytoestablishthedesiredswitchingconfiguration.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit, the Block Programming Data bits, the Begin Block Programming Enable,
theOutputStandBy,StartFrameEvaluation,OutputEnableIndication,andData
Rate Select bits. As explained in the Memory Block Programming section, the
Block Programming Enable begins the programming if the Memory Block
Program bit is enabled. This allows the entire Connection Memory block to be
programmedwiththeBlockProgrammingDatabits.IftheODEpinisLOW,the
OutputStandBybitenables(ifHIGH)ordisables(ifLOW)allTXoutputdrivers.
IftheODEpinisHIGH,theOutputStandBybitisignoredandallTXoutputdrivers
are enabled.
SOFTWARE RESET
The Software Reset serves the same function as the hardware reset. As with
the hard reset, the Software Reset must also be set HIGH for 20ns before
bringingtheSoftwareResetLOWagainfornormaloperation. OncetheSoftware
Reset is LOW, internal registers and other memories may be read or written.
During Software Reset, the microprocessor port is still able to read from all
internal memories. The only write operation allowed during a Software Reset
istotheSoftwareResetbitintheControlRegistertocompletetheSoftwareReset.
CONNECTION MEMORY CONTROL
If the ODE pin and the Output Stand By bit are LOW, all output channels will
be in three-state. See Table 3 for detail.
If MOD1-0 of the Connection Memory is 1-0 accordingly, the output channel
will be in Processor Mode. In this case the lower eight bits of the Connection
Memory are output each frame until the MOD1-0 bits are changed. If MOD
1-0 of the Connection Memory are 0-1 accordingly, the channel will be in
Constant Delay Mode and bits 12-0 are used to address a location in Data
Memory. If MOD1-0 of the Connection Memory are 0-0, the channel will be in
Variable Delay Mode and bits 12-0 are used to address a location in Data
Memory. If MOD 1-0 of the Connection Memory are 1-1, the channel will be
in High-Impedance mode and that channel will be in three-state.
OUTPUT ENABLE INDICATION
TheIDT72V71650hasthecapabilitytoindicatethestateoftheoutputs(active)
orthree-state)byenablingtheOutputEnableIndicationintheControlRegister.
In the Output Enable Indication mode however, only half of the output streams
are available. If this same capability is desired with all 32 streams, this can be
accomplished by using two IDT72V71650 or one IDT72V71660 devices. In
onedevice,theAllOutputEnablebitissettoaonewhileintheothertheAllOutput
Enable is set to zero. In this way, one device acts as the switch and the other
asathree-statecontroldevice,seeFigure4.ItisimportanttonoteiftheTSIdevice
is programmed for All Output Enable and the Output Enable Indication is also
set,thedevicewillbeintheAllOutputEnablemodenotOutputEnableIndication.
INITIALIZATION OF THE IDT72V71650
After power up, the state of the Connection Memory is unknown. As such,
theoutputsshouldbeputinhigh-impedancebyholdingtheODEpinLOW. While
theODEisLOW,themicroprocessorcaninitializethedevicebyusingtheBlock
Programming featureand programtheactivepathsviathemicroprocessorbus.
Once the device is configured, the ODE pin (or Output Stand By bit depending
on initialization) can be switched to enable the TSI switch.
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| IDT72V71660BB | 功能描述:IC DGTL SW 16382X16384 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復用器，解碼器 系列:72V 標準包裝:48 系列:74VHC 類型:多路復用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| IDT72V71660DR | 功能描述:IC DGTL SW 16382X16384 208-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復用器，解碼器 系列:72V 標準包裝:48 系列:74VHC 類型:多路復用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| IDT72V72100L10BB | 功能描述:IC FIFO 131KX36 10NS 256BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V72100L10BBG | 功能描述:IC FIFO 131KX36 10NS 256BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V72100L15BB | 功能描述:IC FIFO 131KX36 15NS 256BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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