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參數(shù)資料
| 型號： | IDT72V70200PFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/23頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL SW 512X512 3.3V 100-TQFP |
| 標準包裝： | 90 |
| 系列： | 72V |
| 類型： | 多路復用器 |
| 電路： | 1 x 16:16 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 72V70200PFG |
3
COMMERCIALTEMPERATURERANGE
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
PIN DESCRIPTION
SYMBOL
NAME
I/O
DESCRIPTION
GND
Ground.
Ground Rail.
Vcc
+3.3 Volt Power Supply.
TX0-15(1)
TX Output 0 to 15
O
Serial data output stream. These streams have a data rate of 2.048 Mb/s.
(Three-state Outputs)
RX0-15(1)
RX Input 0 to 15
I
Serial data input stream. These streams have a data rate of 2.048 Mb/s.
F0i(1)
Frame Pulse
I
This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS
and GCI specifications.
FE(1)
Frame Evaluation
I
Frame measurement input. No pull-up/down. If unused, an external pull-up or pull-down must be provided.
CLK(1)
Clock
I
Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). This input accepts a 4.096 MHz clock.
TMS
Test Mode Select
I
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-
up when not driven.
TDI
Test Serial Data In
I
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
TDO
Test Serial Data Out
O
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enabled.
TCK(1)
Test Clock
I
Provides the clock to the JTAG test logic.
TRST
Test Reset
I
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V70200 is in the normal functional mode.
IC(1)
Internal Connection
I
Connect to GND for normal operation. This pin must be LOW for the IDT72V70200 to function normally and to
comply with IEEE 1114 (JTAG) boundary scan requirements.
RESET(1)
Device Reset
I
This input (active LOW) puts the IDT72V70200 in its reset state that clears the device internal counters, registers
(Schmitt Trigger Input)
and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up
reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the
RESET
pin must be held LOW for a minimum of 100ns to reset the device.
A0-7(1)
Address 0-7
I
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
DS/
RD(1)
Data Strobe/Read
I
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with
CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS.
This active LOW input works in conjunction with
CS to enable the read and write operations. For Intel multiplexed
bus operation, this input is
RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
R/
W / WR(1) Read/Write / Write
I
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/
W. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is
WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.
CS(1)
Chip Select
I
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70200.
AS/ALE(1)
Address Strobe or
I
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
Latch Enable
bus operation, connect this pin to ground.
IM(1)
CPU Interface Mode
I
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
AD0-7(1)
Address/Data Bus 0 to 7 I/O
These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
D8-15(1)
Data Bus 8-15
I/O
These pins are the eight most significant data bits of the microprocessor port.
DTA(1)
Data Transfer
O
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
Acknowledgment
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
CCO(1)
Control Output
O
This is a 4.096 Mb/s output containing 512 bits per frame respectively. The level of each bit is determined by
the CCO bit in the connection memory. See External Drive Control Section.
ODE(1)
Output Drive Enable
I
This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per channel control bit in the connection memory.
NOTE:
1. These pins are 5V tolerant.
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| IDT72V70200PFG8 | 功能描述:IC DGTL SW 512X512 3.3V 100-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復用器，解碼器 系列:72V 標準包裝:48 系列:74VHC 類型:多路復用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
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