參數(shù)資料
型號: IDT72V51456L7-5BBI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 8/57頁
文件大?。?/td> 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
標準包裝: 1
類型: 多隊列流量控制
安裝類型: 表面貼裝
封裝/外殼: 256-BBGA
供應商設(shè)備封裝: 256-BGA(17x17)
包裝: 帶卷 (TR)
其它名稱: 72V51456L7-5BBI
16
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51436/72V51446/72V51456 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0
°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)
tPAELZ(2)
RCLK to
PAE Flag Bus to Low-Impedance
0.6
3.7
0.6
4
ns
tPAEHZ(2)
RCLK to
PAE Flag Bus to High-Impedance
0.6
3.7
0.6
4
ns
tPAFLZ(2)
WCLK to
PAF Flag Bus to Low-Impedance
0.6
3.7
0.6
4
ns
tPAFHZ(2)
WCLK to
PAF Flag Bus to High-Impedance
0.6
3.7
0.6
4
ns
tFFHZ(2)
WCLK to Full Flag to High-Impedance
0.6
3.7
0.6
4
ns
tFFLZ(2)
WCLK to Full Flag to Low-Impedance
0.6
3.7
0.6
4
ns
tOVLZ(2)
RCLK to Output Valid Flag to Low-Impedance
0.6
3.7
0.6
4
ns
tOVHZ(2)
RCLK to Output Valid Flag to High-Impedance
0.6
3.7
0.6
4
ns
tFSYNC
WCLK to
PAF Bus Sync to Output
0.6
3.7
0.6
4
ns
tFXO
WCLK to
PAF Bus Expansion to Output
0.6
3.7
0.6
4
ns
tESYNC
RCLK to
PAE Bus Sync to Output
0.6
3.7
0.6
4
ns
tEXO
RCLK to
PAE Bus Expansion to Output
0.6
3.7
0.6
4
ns
tPR
RCLK to Packet Ready Flag
0.6
3.7
0.6
4
ns
tSKEW1
SKEW
time between RCLK and WCLK for
FF and OV
4.5
5.75
ns
tSKEW2
SKEW
time between RCLK and WCLK for
PAF and PAE
6
7.5
ns
tSKEW3
SKEW
time between RCLK and WCLK for
PAF[0:7] and PAE[0:7]
6
7.5
ns
tSKEW4
SKEW
time between RCLK and WCLK for
PR and OV
6
7.5
ns
tSKEW5
SKEW
time between RCLK and WCLK for
OV when in Packet Mode
10
12
ns
tXIS
Expansion Input Setup
1.0
1.3
ns
tXIH
Expansion Input Hold
0.5
0.5
ns
Commercial
Com'l & Ind'l(1)
IDT72V51436L6
IDT72V51436L7-5
IDT72V51446L6
IDT72V51446L7-5
IDT72V51456L6
IDT72V51456L7-5
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
NOTES:
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
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