參數資料
型號： IDT72V51453L7-5BB8
廠商： IDT, Integrated Device Technology Inc
文件頁數： 27/50頁
文件大?。?/td> 0K
描述： IC FLOW CTRL MULTI QUEUE 256-BGA
標準包裝： 1,000
類型： 多隊列流量控制
安裝類型： 表面貼裝
封裝/外殼： 256-BBGA
供應商設備封裝： 256-BGA（17x17）
包裝： 帶卷 (TR)
其它名稱： 72V51453L7-5BB8
33
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
WADEN
tQH
tQS
tAH
tAS
WRADD
D
1
Q
12
FF (Device
1)
tFFLZ
5939
drw13
WEN
tENS
tAH
tAS
tAH
tAS
tQH
tQS
D
2
Q
9
tQH
tQS
tDH
tDS
W
D
1
Q12
tDH
tDS
Din
tWFF
HIGH-Z
RCLK
1
2
tENH
tENS
tENH
Addr=001
1100
D
1
Q
5
tWFF
W
D
1
Q5
tFFHZ
tWFF
HIGH-Z
FF (Device
2)
tFFHZ
HIGH-Z
tFFLZ
tSKEW1
Addr=001
0101
tAH
tAS
RDADD
D
1
Q
5
tQH
tQS
RADEN
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
No
Write
*J*
Qout
tA
Previous
Q
W
X-1
Previous
Q
W
X
PFT
D
1
-Q
5
Word
W
0
PFT
*AA*
*BB*
*CC*
Figure
11.
Full
Flag
Timing
in
Expansion
Mode
NOTE:
1.
REN
=
HIGH.
Cycle
:
*A*
Queue,
Q12
of
device
1
is
selected
on
the
write
port.
The
FF
flag
of
device
1
is
in
High-Impedance,
the
write
port
of
device
2
was
previously
selected.
WEN
is
HIGH
so
no
write
occurs.
*AA*
Queue,
Q5
of
device
1
is
selected
on
the
read
port.
*B*
The
FF
flag
of
device
2
goes
to
High-Impedance
and
the
FF
flag
of
device
1
goes
to
Low-Impedance,
logic
HIGH
indicating
that
D1
Q12
is
not
full.
WEN
is
HIGH
so
no
write
occurs.
*BB*
Word,
Wx
is
read
from
the
previously
selected
queue,
(due
to
FWFT).
*C*
Word,
Wd
is
written
into
Q12
of
D1.
This
write
operation
causes
Q12
to
go
full,
FF
goes
LOW.
*CC*
The
first
word
from
Q5
of
D1
selected
on
cycle
*AA*
is
read
out,
this
occurred
regardless
of
REN
due
to
FWFT.
This
read
caused
Q5
to
go
not
full,
therefore
the
FF
flag
will
go
HIGH
after:
t
SKEW1
+
t
WFF
.
Note
if
t
SKEW1
is
violated
the
time
to
FF
flag
HIGH
is
t
SKEW1
+
WLCK
+
t
WFF
.
*D*
Queue,
Q5
of
device
1
is
selected
on
the
write
port.
No
write
occurs
on
this
cycle.
*E*
The
FF
flag
updates
to
show
the
status
of
D1
Q5,
it
is
not
full,
FF
goes
HIGH.
*F*
Word,
Wd
is
written
into
Q5
of
D1.
This
causes
the
queue
to
go
full,
FF
goes
LOW.
*G*
No
write
occurs
regardless
of
WEN
,the
FF
flag
is
LOW
preventing
writes.
*H*
The
FF
flag
goes
HIGH
due
to
the
read
from
Q5
of
D1
on
cycle
*CC*.
(This
read
is
not
an
enabled
read,
it
is
due
to
the
FWFT
operation
).
*I*
Queue,
Q9
of
device
2
is
selected
on
the
write
port.
*J*
The
FF
flag
of
device
1
goes
to
High-Impedance,
this
device
was
deselected
on
the
write
port
on
cycle
*I*.
The
FF
flag
of
device
2
goes
to
Low-Impedance
and
provides
status
of
Q9
of
D2.
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