參數(shù)資料
型號: IDT72V51256L6BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 4/56頁
文件大?。?/td> 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
標準包裝: 1
類型: 多隊列流量控制
安裝類型: 表面貼裝
封裝/外殼: 256-BBGA
供應商設備封裝: 256-BGA(17x17)
包裝: 托盤
其它名稱: 72V51256L6BB
12
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O TYPE
Description
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 51-55 and Figures 31-33.
WEN
WriteEnable
LVTTL
The
WEN input enables write operations to a selected queue based on a rising edge of WCLK.
INPUT
A queue to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless
of the state of
WEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLK
cycle after queue selection provided that
WEN is LOW. A write enable is not required to cycle the PAFn
bus (in polled mode) or to select the device , (in direct mode).
WRADD
Write Address Bus
LVTTL
For the 4Q device the WRADD bus is 5 bits. The WRADD bus is a dual purpose address bus. The first
[4:0]
INPUT
functionofWRADDistoselectaqueuetobewrittento.Theleastsignificant2bitsofthebus,WRADD[1:0]
are used to address 1 of 4 possible queues within a multi-queue device. The most significant 3bits,
WRADD[4:2] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSb’s will address a device with the matching ID code. The address present on the
WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data
present on the Din bus can be written into the previously selected queue on this WCLK edge and on the
next rising WCLK also, providing that
WEN is LOW). Two WCLK rising edges after write queue select,
data can be written into the newly selected queue.
The second function of the WRADD bus is to select the device of queues to be loaded on to the
PAFn
bus during strobed flag mode. The most significant 3 bits, WRADD[4:2] are again used to select 1 of 8
possible multi-queue devices that may be connected in expansion mode. Address bits WRADD[1:0]
are don’t care during device selection. The device address present on the WRADD bus will be selected
on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be written into the previously
selected queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus.
VCC
+3.3V Supply
Power
These are VCC power supply pins and must all be connected to a +3.3V supply rail.
GND
Ground Pin
Ground
These are Ground pins and must all be connected to the GND supply rail.
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