參數(shù)資料
型號： IDT72V51246L7-5BB
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 19/56頁
文件大?。?/td> 0K
描述： IC FLOW CTRL MULTI QUEUE 256-BGA
標準包裝： 1
類型： 多隊列流量控制
安裝類型： 表面貼裝
封裝/外殼： 256-BBGA
供應商設備封裝： 256-BGA（17x17）
包裝： 托盤
其它名稱： 72V51246L7-5BB
26
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion:
Read Operation to
PAEn LOW: 2 RCLK* + tPAE
De-assertion: Write to
PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
Programmable Almost Empty Flag Bus,
PAEn Boundary
I/O Set-Up
PAEn Boundary Condition
in36 to out36
PAEn Goes HIGH after
(Both ports selected for same queue when the 1st
n+2 Writes
Word is written in until the boundary is reached)
(see note below for timing)
in36 to out36
PAEn Goes HIGH after
(Write port only selected for same queue when the n+1 Writes
1st Word is written in until the boundary is reached) (see note below for timing)
in36 to out18
PAEn Goes HIGH after n+1
Writes (see below for timing)
in36 to out9
PAEn Goes HIGH after n+1
Writes (see below for timing)
in18 to out36
PAEn Goes HIGH after
(Both ports selected for same queue when the 1st
([n+2] x 2) Writes
Word is written in until the boundary is reached)
(see note below for timing)
in18 to out36
PAEn Goes HIGH after
(Write port only selected for same queue when the ([n+1] x 2) Writes
1st Word is written in until the boundary is reached) (see note below for timing)
in9 to out36
PAEn Goes HIGH after
(Both ports selected for same queue when the 1st
([n+2] x 4) Writes
Word is written in until the boundary is reached)
(see note below for timing)
in9 to out36
PAEn Goes HIGH after
(Write port only selected for same queue when the ([n+1] x 4) Writes
1st Word is written in until the boundary is reached) (see note below for timing)
NOTE:
n = Almost Empty Offset value.
Default values:
if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAE Timing
Assertion:
Read Operation to
PAE LOW: 2 RCLK + tRAE
De-assertion: Write to
PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
Programmable Almost Empty Flag,
PAE Boundary
I/O Set-Up
PAE Assertion
in36 to out36
PAE Goes HIGH after n+2
(Both ports selected for same queue when the 1st
Writes
Word is written in until the boundary is reached)
(see note below for timing)
in36 to out18
PAE Goes HIGH after n+1
(Both ports selected for same queue when the 1st
Writes
Word is written in until the boundary is reached)
(see note below for timing)
in36 to out9
PAE Goes HIGH after n+1
(Both ports selected for same queue when the 1st
Writes
Word is written in until the boundary is reached)
(see note below for timing)
in18 to out36
PAE Goes HIGH after
(Both ports selected for same queue when the 1st
([n+2] x 2) Writes
Word is written in until the boundary is reached)
(see note below for timing)
in9 to out36
PAE Goes HIGH after
(Both ports selected for same queue when the 1st
([n+2] x 4) Writes
Word is written in until the boundary is reached)
(see note below for timing)
PACKET READY FLAG,
PR BOUNDARY
Assertion:
Both the rising and falling edges of
PR are synchronous to RCLK.
PR Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assuming a TSOP marker, on input D34 has previously been written). i.e. a
complete packet is available within a queue.
Timing:
From WCLK rising edge writing the TEOP word
PR goes LOW after: tSKEW4
+ 2 RCLK + tPR
If tSKEW4 is violated:
PR goes LOW after tSKEW4 + 3 RCLK + tPR
(Please refer to Figure 18, Data Input (Transmit) Packet Mode of Operation
for timing diagram).
De-assertion:
PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34.
i.e. there are no more complete packets available within the queue.
Timing:
From RCLK rising edge Reading the RSOP word the
PR goes HIGH after:
2 RCLK + tPR
(Please refer to Figure 19, Data Output (Receive) Packet Mode of Operation
for timing diagram).
PACKET READY FLAG BUS,
PRn BOUNDARY
Assertion:
Both the rising and falling edges of
PRn are synchronous to RCLK.
PRn Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assuming a TSOP marker, on input D34 has previously been written). i.e. a
complete packet is available within a queue.
Timing:
From WCLK rising edge writing the TEOP word
PR goes LOW after: tSKEW4
+ 2 RCLK* + tPAE
If tSKEW4 is violated
PRn goes LOW after tSKEW4 + 3 RCLK* + tPAE
*Ifaqueueswitchisoccurringonthereadportatthepointofflagassertionthere
may be one additional RCLK clock cycle delay.
De-assertion:
PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34.
i.e. there are no more complete packets available within the queue.
Timing:
From RCLK rising edge Reading the RSOP word the
PR goes HIGH after: 2
RCLK* + tPAE
*If a queue switch is occurring on the read port at the point of flag assertion or
de-assertion there may be one additional RCLK clock cycle delay.
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