IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72V3670L7-5BBI
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 28/46闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FIFO SS 8192X36 7-5NS 144BGA
妯欐簴鍖呰锛� 1
绯诲垪锛� 72V
鍔熻兘锛� 鐣版锛屽悓姝�
瀛樺劜瀹归噺锛� 288K锛�8K x 36锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 133MHz
瑷晱鏅傞枔锛� 5ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 144-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-PBGA锛�13x13锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 72V3670L7-5BBI
34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768
for the IDT72V3690.
In FWFT mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the
IDT72V3690.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the
PAF deassertion time may be delayed one extra WCLK cycle.
4.
PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
WCLK
WEN
PAF
RCLK
(3)
tPAFS
REN
4667 drw23
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
1
2
12
D-(m+1) words
in FIFO(2)
tPAFS
tENH
tENS
tSKEW2
tENH
tENS
tCLKL
RCLK
LD
REN
Q0 - Qn
tLDH
tLDS
tENS
DATA IN OUTPUT REGISTER
PAE OFFSET
PAF OFFSET
tENH
tLDH
4667 drw22
t CLK
tA
tCLKH
tCLKL
WCLK
LD
WEN
D0 - Dn
4667 drw21
tLDS
tENS
PAE
OFFSET
PAF
OFFSET
tDS
tDH
tLDH
tENH
tCLK
tLDH
tENH
tDH
tCLKH
tCLKL
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
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