IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
  • 參數(shù)資料
    型號(hào): IDT72V3660L7-5PF
    廠商: IDT, Integrated Device Technology Inc
    文件頁數(shù): 27/46頁
    文件大?。?/td> 0K
    描述: IC FIFO SS 4096X36 7-5NS 128TQFP
    標(biāo)準(zhǔn)包裝: 36
    系列: 72V
    功能: 異步,同步
    存儲(chǔ)容量: 147K(4K x 36)
    數(shù)據(jù)速率: 133MHz
    訪問時(shí)間: 5ns
    電源電壓: 3.15 V ~ 3.45 V
    工作溫度: 0°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 128-LQFP
    供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
    包裝: 托盤
    其它名稱: 72V3660L7-5PF
    33
    COMMERCIAL AND INDUSTRIAL
    TEMPERATURE RANGES
    IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
    1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
    OCTOBER 22, 2008
    Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
    NOTE:
    1. X = 9 for the IDT72V3640, X = 10 for the IDT72V3650, X = 11 for the IDT72V3660, X = 12 for the IDT72V3670, X = 13 for the IDT72V3680 and X = 14 for the IDT72V3690.
    NOTES:
    1. If the part is empty at the point of Retransmit, the output ready flag (
    OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
    2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore,
    IR will be LOW throughout the Retransmit setup procedure.
    D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690.
    3.
    OE = LOW.
    4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
    5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
    6. RM is set LOW during MRS.
    Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
    WCLK
    SEN
    SI
    4667 drw20
    tENH
    tENS
    tLDS
    LD
    tDS
    BIT 0
    EMPTY OFFSET
    BIT X
    BIT 0
    FULL OFFSET
    (1)
    tENH
    BIT X
    (1)
    tLDH
    tDH
    tLDH
    tRTS
    tENH
    4667 drw19
    tENS
    Wx
    WCLK
    RCLK
    REN
    RT
    OR
    PAF
    HF
    PAE
    Q0 - Qn
    tSKEW2
    12
    1
    tPAFS
    tHF
    tPAES
    Wx+1
    2
    W3
    WEN
    tENS
    W2
    (4)
    4
    5
    tENH
    W4
    tA
    W5
    tA
    (4)
    3
    tA
    W1
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