IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM WITH BUS MATCH" />
參數(shù)資料
型號: IDT72V3656L15PF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 14/39頁
文件大?。?/td> 0K
描述: IC SYNC FIFO 4096X36 15NS 128QFP
標(biāo)準(zhǔn)包裝: 36
系列: 72V
功能: 異步
存儲容量: 147K(4K x 36)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 72V3656L15PF
21
COMMERCIALTEMPERATURERANGE
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Figure 9. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for
FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then
FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until
FFA/IRA, FFC/IRC is set HIGH.
3. Programmable offsets are written serially to the SD input in the order
AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for
FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then
FFC/IRC may transition HIGH one CLKC cycle later than shown.
2.
CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
Figure 8. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
4665 drw09
CLKA
MRS1,
MRS2
FFA/IRA
CLKC
FFC/IRC
A0-A35
FS1,FS0
ENA
tFSH
tWFF
tENH
tENS2
tSKEW1
tDS
tDH
tWFF
4
0,0
AFA Offset
(Y1)
AEB Offset
(X1)
AFC Offset
(Y2)
AEA Offset
(X2)
First Word to FIFO1
1
2
(1)
tFSH
tFSS
FS2
CLKA
FFA/IRA
tSENS
tSENH
FS0/SD(3)
tSPH
tSENS
tSENH
tFSS
tWFF
FS1/SEN
AEA Offset
(X2) LSB
tSDS
tSDH
tSDS
tSDH
AFA Offset
(Y1) MSB
MRS1,
MRS2
4
4665 drw 10
tFSS
tFSH
CLKC
4
FS2
FFC/IRC
tWFF
tSKEW(1)
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