27
COMMERCIALTEMPERATURERANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
CLKA
ENB
CLKB
RT
4662 drw 21
tRSTS
tRSTH
tREF
(2)
B0-Bn
RTM
EF
tREF
(2)
W1
Wx
tA
tENS2
tENH
13
4
2
1
34
2
tRTMS
tRTMH
CLKA
ENB
CLKB
RT
4662 drw22
tRSTS
tRSTH
tREF
(2)
B0-Bn
RTM
OR
tREF
(2)
W1
Wx
tA
13
4
2
1
34
2
tRTMS
tRTMH
LOW
NOTE:
1. CSB = LOW; W/RB is HIGH
2. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO after Master Reset.
4. No more than D-2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be LOW throughout the Retransmit setup procedure.
D = 2,048, 4,096 and 8,192 for the IDT72V3653. 72V3663 and 72V3673 respectively.
Figure 19. Retransmit Timing (IDT Standard Mode)
NOTE:
1. CSB = LOW; W/RB is HIGH
2. Retransmit setup is complete after OR returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO after Master Reset.
4. No more than D-2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 2,048, 4,096 and 8,192 for the IDT72V3653. 72V3663 and 72V3673 respectively.
Figure 20. Retransmit Timing (FWFT Mode)