參數(shù)資料
型號(hào): IDT72V3651L15PQF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 19/21頁(yè)
文件大?。?/td> 0K
描述: IC SYNCFIFO 2048X36 15NS 132PQFP
標(biāo)準(zhǔn)包裝: 36
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 72K(2K x 36)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 132-BQFP 緩沖式
供應(yīng)商設(shè)備封裝: 132-PQFP(24.13x24.13)
包裝: 托盤
其它名稱: 72V3651L15PQF
7
COMMERCIALTEMPERATURERANGE
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO 512 x 36, 1,024 x 36 and 2,048 x 36
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3631L15
IDT72V3631L20
IDT72V3641L15
IDT72V3641L20
IDT72V3651L15
IDT72V3651L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
66.7
50
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
15
20
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
6
8
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
6
8
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and B0-B35
5
6
ns
before CLKB
tENS1
Setup Time, ENA to CLKA
↑;ENBtoCLKB↑
5–
6
ns
tENS2
Setup Time,
CSA, W/RA, and MBA to CLKA
↑;
7
7.5
ns
CSB, W/RB, and MBB to CLKB
tRMS
Setup Time, RTM and RFM to CLKB
6
6.5
ns
tRSTS
Setup Time,
RST LOW before CLKA
5–
6
ns
or CLKB
(1)
tFSS
Setup Time, FS0 and FS1 before
RST HIGH
9
10
ns
tSDS(2)
Setup Time, FS0/SD before CLKA
5–
6
ns
tSENS(2)
Setup Time, FS1/
SEN before CLKA
5–
6
ns
tDH
Hold Time, A0-A35 after CLKA
↑ and B0-B35
0.5
0.5
ns
afterCLKB
tENH1
Hold Time, ENA after CLKA
↑;ENBafterCLKB↑
0.5
0.5
ns
tENH2
Hold Time,
CSA, W/RA, and MBA after CLKA
↑;
0.5
0.5
ns
CSB, W/RB, and MBB after CLKB
tRMH
Hold Time, RTM and RFM after CLKB
0.5
0.5
ns
tRSTH
Hold Time,
RST LOW after CLKA
↑ or CLKB↑(1)
5–
6
ns
tFSH
Hold Time, FS0 and FS1 after
RST HIGH
0
0
ns
tSPH(2)
Hold Time, FS1/
SEN HIGH after RST HIGH
0
0
ns
tSDH(2)
Hold Time, FS0/SD after CLKA
0–
0
ns
tSENH(2)
Hold Time, FS1/
SEN after CLKA
0–
0
ns
tSKEW1(3)
Skew Time, between CLKA
↑andCLKB↑
9–
11
ns
for OR and IR
tSKEW2(3,4)
Skew Time, between CLKA
↑andCLKB↑
12
16
ns
for
AE and AF
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Only applies when serial load method is used to program flag Offset registers.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
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