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| 型號(hào)： | IDT72V3643L10PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNCFIFO 1024X36 10NS 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲(chǔ)容量： | 36.8K（1K x 36） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時(shí)間： | 10ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3643L10PF |
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10
IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURERANGE
significant byte (word) of the long word written to Port A will be read from Port
B first; the least significant byte (word) of the long word written to Port A will be
read from Port B last.
ALOWontheBE/
FWFTinputwhentheReset(RS1)inputgoesfromLOW
toHIGHwillselectaLittle-Endianarrangement. Inthiscase,theleastsignificant
byte (word) of the long word written to Port A will be read from Port B first; the
most significant byte (word) of the long word written to Port A will be read from
Port B last. Refer to Figure 2 for an illustration of the BE function. See Figure
3 (Reset) for an Endian select timing diagram.
— TIMING MODE SELECTION
AfterReset,theFWFTselectfunctionisactive,permittingachoicebetween
two possible timing modes: IDT Standard mode or First Word Fall Through
(FWFT) mode. Once the Reset (
RS1)inputisHIGH,aHIGHontheBE/FWFT
input during the next LOW-to-HIGH transition of CLKA and CLKB will select
IDT Standard mode. This mode uses the Empty Flag function (
EF)toindicate
whether or not there are any words present in the FIFO memory. It uses the
FullFlagfunction(
FF)toindicatewhetherornottheFIFOmemoryhasanyfree
space for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using a formal read operation.
OncetheReset(
RS1)inputisHIGH,aLOWontheBE/FWFTinputduring
the next LOW-to-HIGH transition of CLKA and CLKB will select FWFT mode.
ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere
is valid data at the data outputs (B0-B35). It also uses the Input Ready function
(IR) to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Reset, the level applied to the BE/
FWFT input to choose the
desired timing mode must remain static throughout FIFO operation. Refer to
Figure 3 (Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
TworegistersintheIDT72V3623/72V3633/72V3643areusedtoholdthe
offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags. TheAlmost-Emptyflag
(
AE)OffsetregisterislabeledXandAlmost-Fullflag(AF)Offsetregisterislabeled
Y. The offset registers can be loaded with preset values during the reset of the
FIFO, programmed in parallel using the FIFO’s Port A data inputs, or
programmedinserialusingtheSerialData(SD)input(seeTable1).
SPM,FS0/
SD, and FS1/
SEN function the same way in both IDT Standard and FWFT
modes.
— PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers
with one of the three preset values listed in Table 1, the Serial Program Mode
(
SPM)andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-
to-HIGH transition of the Reset input (
RS1). For example, to load the preset
value of 64 into X and Y,
SPM,FS0andFS1mustbeHIGHwhen RS1returns
HIGH. For the relevant preset value loading timing diagram, see Figure 3.
— PARALLEL LOAD FROM PORT A
To program the X and Y registers from Port A, perform a Reset on with
SPMHIGHandFS0andFS1LOWduringtheLOW-to-HIGHtransitionofRS1.
After this reset is complete, the first two writes to the FIFO do not store data in
RAM. The first two write cycles load the offset registers in the order Y, X. On
SIGNAL DESCRIPTION
RESET (
RS1, RS2)
Afterpowerup,aResetoperationmustbeperformedbyprovidingaLOW
pulse to
RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the
IDT72V3623/72V3633/72V3643 undergoes a complete reset by taking its
Reset (
RS1andRS2)inputLOWforatleastfourPortAclock(CLKA)andfour
Port B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch
asynchronously to the clocks. A Reset initializes the internal read and write
pointers and forces the Full/Input Ready flag (
FF/IR)LOW,theEmpty/Output
Ready flag (
EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-
Full flag (
AF)HIGH. AReset(RS1)alsoforcestheMailboxflag(MBF1)ofthe
parallelmailboxregisterHIGH,andatthesametimethe
RS2andMBF2operate
likewise. After a Reset, the FIFO’s Full/Input Ready flag is set HIGH after two
write clock cycles to begin normal operation.
ALOW-to-HIGHtransitionontheFlFOReset(
RS1)inputlatchesthevalue
of the Big-Endian (BE) input for determining the order by which bytes are
transferred through Port B.
ALOW-to-HIGHtransitionontheFlFOReset(
RS1)inputalsolatchesthe
values of the Flag Select (FS0, FS1) and Serial Programming Mode (
SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method ( for details see Table 1, Flag Programming, and Almost-Empty and
Almost-Fullflagoffsetprogrammingsection). TherelevantResettimingdiagram
can be found in Figure 3.
PARTIAL RESET (
PRS)
The FIFO memory of the IDT72V3623/72V3633/72V3643 undergoes a
limited reset by taking its Partial Reset (
PRS)inputLOWforatleastfourPortA
clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The
Partial Reset input can switch asynchronously to the clocks. A Partial Reset
initializes the internal read and write pointers and forces the Full/Input Ready
flag (
FF/IR) LOW, the Empty/Output Ready flag (EF/OR) LOW, the Almost-
Emptyflag(
AE)LOW,andtheAlmost-Fullflag(AF)HIGH. APartialResetalso
forces the Mailbox flag (
MBF1, MBF2) of the parallel mailbox register HIGH.
AfteraPartialReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoWrite
Clock cycles to begin normal operation. See Figure 4, Partial Reset (IDT
Standard and FWFT Modes) for the relevant timing diagram.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Reset would be inconvenient.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT)
— ENDIAN SELECTION
This is a dual purpose pin. At the time of Reset, the BE select function is
active,permittingachoiceofBig-orLittle-Endianbytearrangementfordataread
from Port B. This selection determines the order by which bytes (or words) of
dataaretransferredthroughthisport. Forthefollowingillustrations,assumethat
a byte (or word) bus size has been selected for Port B. (Note that when Port
B is configured for a long word size, the Big-Endian function has no application
and the BE input is a “don’t care”1.)
A HIGH on the BE/
FWFT input when the Reset (RS1) input goes from
LOW to HIGH will select a Big-Endian arrangement. In this case, the most
NOTE:
1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
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| IDT72V3643L10PF8 | 功能描述:IC SYNCFIFO 1024X36 10NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3643L15PF | 功能描述:IC SYNCFIFO 1024X36 15NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3643L15PF8 | 功能描述:IC SYNCFIFO 1024X36 15NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3644L10PF | 功能描述:IC FIFO 2048X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3644L10PF8 | 功能描述:IC FIFO 2048X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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