- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9978 > IDT72V3642L15PF (IDT, Integrated Device Technology Inc)IC FIFO 1MX72 15NS 120QFP PDF資料下載
參數(shù)資料
| 型號： | IDT72V3642L15PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 1MX72 15NS 120QFP |
| 標準包裝： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 72k（1k x 36 x 2） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應商設備封裝： | 120-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3642L15PF |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
10
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
FollowingReset,thelevelappliedtotheFWFTinputtochoosethedesired
timingmodemustremain staticthroughoutFIFOoperation.RefertoFigure2
(Reset) for a First Word Fall Through select timing diagram.
ALMOST-EMPTYFLAGANDALMOST-FULLFLAGOFFSETPROGRAM-
MING
Four registers in these devices are used to hold the offset values for the
Almost-EmptyandAlmost-Fullflags.TheportBAlmost-Emptyflag(AEB)Offset
register is labeled X1 and the port A Almost-Empty flag (AEA) Offset register
is labeled X2. The port A Almost-Full flag (AFA) Offset register is labeled Y1
and the port B Almost-Full flag (AFB) Offset register is labeled Y2. The index
ofeachregisternamecorrespondstoitsFIFOnumber.Theoffsetregisterscan
be loaded with preset values during the reset of a FIFO or they can be
programmed from port A (see Table 1).
FS0 and FS1 function the same way in both IDT Standard and FWFT
modes.
— PRESET VALUES
ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisters
withoneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselect
inputsmustbeHIGHduringtheLOW-to-HIGHtransitionofitsresetinput.For
example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be
HIGH when FlFO1 Reset (RST1) returns HIGH. Flag offset registers
associatedwithFIFO2areloadedwithoneofthepresetvaluesinthesameway
withFIFO2Reset(RST2)toggledsimultaneouslywithFIFO1Reset(RST1).
For preset value loading timing diagram, see Figure 2.
— PARALLEL LOAD FROM PORT A
ToprogramtheX1,X2,Y1,andY2registersfromportA,bothFlFOsshould
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transitionoftheResetinputs.Afterthisresetiscomplete,thefirstfourwritesto
FIFO1donotstoredataintheFIFOmemorybutloadtheoffsetregistersinthe
order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are
(A7-A0), (A8-A0), or (A9-A0) for the IDT72V3622, IDT72V3632, or
IDT72V3642, respectively. The highest numbered input is used as the most
significantbitofthebinarynumberineachcase. Validprogrammingvaluesfor
the registers ranges from 1 to 252 for the IDT72V3622; 1 to 508 for the
IDT72V3632;and1to1,020fortheIDT72V3642. Afteralltheoffsetregisters
areprogrammedfromportA,theportBFull/InputReadyflag(FFB/IRB)isset
HIGH,andbothFIFOsbeginnormaloperation.SeeFigure3forrelevantoffset
registerparallelprogrammingtimingdiagram.
SIGNAL DESCRIPTION
RESET
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding
a LOW pulse to RST1 and RST2 simultaneously. Afterwards, the FIFO
memories of the IDT72V3622/72V3632/72V3642 are reset separately by
taking their Reset (RST1, RST2) inputs LOW for at least four port-A Clock
(CLKA) and four port-B Clock (CLKB) LOW-to-HIGH transitions. The Reset
inputs can switch asynchronously to the clocks. A FIFO reset initializes the
internalreadandwritepointersandforcestheInputReadyflag(IRA,IRB)LOW,
theOutputReadyflag(ORA,ORB)LOW,theAlmost-Emptyflag(AEA,AEB)
LOW,andtheAlmost-Fullflag(AFA,AFB)HIGH. ResettingaFIFOalsoforces
the Mailbox Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After
aFIFOisreset,itsInputReadyflagissetHIGHaftertwoclockcyclestobegin
normaloperation.
ALOW-to-HIGHtransitiononaFIFOReset(RST1,RST2)inputlatches
thevalueoftheFlagSelect(FS0,FS1)inputsforchoosingtheAlmost-Fulland
Almost-Empty offset programming method. (For details see Table 1, Flag
Programming,andtheProgrammingtheAlmost-EmptyandAlmost-FullFlags
section). The relevant FIFO Reset timing diagram can be found in Figure 2.
FIRST WORD FALL THROUGH (FWFT)
AfterMasterReset,theFWFTselectfunctionisactive,permittingachoice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Reset (RST1, RST2) input is HIGH, a
HIGH on the FWFT input during the next LOW-to-HIGH transition of CLKA
(for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (EFA, EFB) to indicate whether or not there
areanywordspresentintheFIFOmemory.ItusestheFullFlagfunction(FFA,
FFB) to indicate whether or not the FIFO memory has any free space for
writing. In IDT Standard mode, every word read from the FIFO, including the
first, must be requested using a formal read operation.
Once the Reset (RST1, RST2) input is HIGH, a LOW on the FWFT input
during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for
FIFO2) will select FWFT mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at the data outputs
(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)toindicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodataoutputs,no
readrequestnecessary. Subsequentwordsmustbeaccessedbyperforming
a formal read operation.
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
FS1
FS0
RST1
RST2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
HH
↑
X64
X
HH
X
↑
X64
HL
↑
X16
X
HL
X
↑
X16
LH
↑
X8
X
LH
X
↑
X8
LL
↑↑
Parallel programming via Port A
TABLE 1 — FLAG PROGRAMMING
相關PDF資料 |
PDF描述 |
|---|---|
| MS27468T21F41PB | CONN RCPT 41POS JAM NUT W/PINS |
| MS27656T23A55PB | CONN RCPT 55POS WALL MNT W/PINS |
| VI-BWH-MY | CONVERTER MOD DC/DC 52V 50W |
| VI-BNZ-MW | CONVERTER MOD DC/DC 2V 40W |
| VI-BNV-MY | CONVERTER MOD DC/DC 5.8V 50W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V3642L15PF8 | 功能描述:IC FIFO 1MX72 15NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3642L15PQF | 功能描述:IC FIFO 1MX72 15NS 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3643L10PF | 功能描述:IC SYNCFIFO 1024X36 10NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3643L10PF8 | 功能描述:IC SYNCFIFO 1024X36 10NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3643L15PF | 功能描述:IC SYNCFIFO 1024X36 15NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
發(fā)布緊急采購，3分鐘左右您將得到回復。