IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� IDT72V3634L15PF8
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 34/34闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FIFO 512X36X2 15NS 128QFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
绯诲垪锛� 72V
鍔熻兘锛� 鐣版锛屽悓姝�
瀛樺劜(ch菙)瀹归噺锛� 36.8K锛�512 x 36 x 2锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 67MHz
瑷晱鏅�(sh铆)闁擄細 15ns
闆绘簮闆诲锛� 3 V ~ 3.6 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 128-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 128-TQFP锛�14x20锛�
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� 72V3634L15PF8
9
COMMERCIALTEMPERATURERANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF
IDT72V3624L10(1)
IDT72V3624L15
IDT72V3634L10(1)
IDT72V3634L15
IDT72V3644L10(1)
IDT72V3644L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
tA
Access Time, CLKA
鈫� toA0-A35andCLKB鈫� toB0-B35
2
6.5
2
10
ns
tWFF
Propagation Delay Time, CLKA
鈫� to FFA/IRA and CLKB鈫� to FFB/IRB
2
6.5
2
8
ns
tREF
Propagation Delay Time, CLKA
鈫� to EFA/ORA and CLKB鈫� to EFB/ORB
1
6.5
1
8
ns
tPAE
Propagation Delay Time, CLKA
鈫� to AEA and CLKB鈫� to AEB
1
6.5
1
8
ns
tPAF
Propagation Delay Time, CLKA
鈫� to AFA and CLKB鈫� to AFB
1
6.5
1
8
ns
tPMF
Propagation Delay Time, CLKA
鈫� to MBF1 LOW or MBF2 HIGH and CLKB鈫�
0
6.5
0
8
ns
to
MBF2 LOW or MBF1 HIGH
tPMR
Propagation Delay Time, CLKA
鈫� to B0-B35(2)and CLKB鈫� to A0-A35(3)
28
2
10
ns
tMDV
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 valid
2
6.5
2
10
ns
tRSF
Propagation Delay Time,
MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and
1
10
1
15
ns
MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, and MBF2
HIGH
tEN
Enable Time,
CSA or W/RA LOW to A0-A35 Active and CSB LOW and W/RB
2
6
2
10
ns
HIGH to B0-B35 Active
tDIS
Disable Time,
CSA or W/RA HIGH to A0-A35 at high-impedance and CSB
16
1
8
ns
HIGH or
W/RB LOW to B0-B35 at HIGH impedance
NOTES:
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0
掳 to +70掳C; JEDEC JESD8-A compliant.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Industrial temperature range is available by special order.
Commercial: VCC = 3.3V +/- 0.30V; for 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V ; TA = 0
掳C to +70掳C; JEDEC JESD8-A compliant
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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