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參數(shù)資料
| 型號： | IDT72V3632L10PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/29頁 |
| 文件大小： | 0K |
| 描述： | IC BIFIFO 512X36X2 10NS 120-TQFP |
| 標準包裝： | 45 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲容量： | 36.8K（512 x 36 x 2） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時間： | 10ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應商設備封裝： | 120-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3632L10PF |
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COMMERCIAL TEMPERATURERANGE
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
bythecontentsofregisterY1forAFAandregisterY2forAFB.Theseregisters
are loaded with preset values during a FlFO reset or programmed from port
A (see Almost-Empty flag and Almost-Full flag offset programming section).
AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthan
orequalto(256-Y),(512-Y),or(1,024-Y)fortheIDT72V3622,IDT72V3632,
or IDT72V3642 respectively. An Almost-Full flag is HIGH when the number
of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or
[1,024-(Y+1)] for the IDT72V3622, IDT72V3632, or IDT72V3642 respec-
tively. NotethatadatawordpresentintheFIFOoutputregisterhasbeenread
frommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
arerequiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewlevelof
fill.Therefore,theAlmost-FullflagofaFIFOcontaining[256/512/1,024-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in memory to [256/
512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH
transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber
ofwordsinmemoryto[256/512/1,024-(Y+1)]. ALOW-to-HIGHtransitionofan
Almost-Fullflagsynchronizingclockbeginsthefirstsynchronizationcycleifit
occursattimetSKEW2orgreaterafterthereadthatreducesthenumberofwords
inmemoryto[256/512/1,024-(Y+1)]. Otherwise,thesubsequentsynchroniz-
ingclockcyclemaybethefirstsynchronizationcycle (seeFigures18and19).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
informationbetweenportAandportBwithoutputtingitinqueue.TheMailbox
select(MBA,MBB)inputschoosebetweenamailregisterandaFIFOforaport
datatransferoperation.ALOW-to-HIGHtransitiononCLKAwritesA0-A35data
to the mail1 register when a port A Write is selected by CSA, W/RA, and ENA
andwithMBAHIGH.ALOW-to-HIGHtransitiononCLKBwritesB0-B35data
to the mail2 register when a port B Write is selected by CSB,W/RB,andENB
andwithMBBHIGH.Writingdatatoamailregistersetsitscorrespondingflag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while
themailflagisLOW.
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthemail
register when the port mailbox select input is HIGH. The Mail1 Register Flag
(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhenaportBRead
isselectedbyCSB,W/RB,andENBandwithMBBHIGH.TheMail2Register
Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port
A read is selected by CSA, W/RA, and ENA and with MBA HIGH. The data
inamailregisterremainsintactafteritisreadandchangesonlywhennewdata
iswrittentotheregister.FormailregisterandMailRegisterFlagtimingdiagrams,
see Figure 20 and 21.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array. For both FWFT and IDT Standard modes, each time
awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock.Therefore,aFull/InputReadyflagisLOWiflessthantwo
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe
next memory write location has been read. The second LOW-to-HIGH
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets
the Full/Input Ready flag HIGH.
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcyclecan
bethefirstsynchronizationcycle(seeFigures12through15forFFA/IRAand
FFB/IRB timing diagrams).
ALMOST-EMPTY FLAGS (AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
datafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX1forAEBandregister
X2forAEA.TheseregistersareloadedwithpresetvaluesduringaFIFOreset
orprogrammedfromportA(seeAlmost-EmptyflagandAlmost-Fullflagoffset
programmingsection).AnAlmost-EmptyflagisLOWwhenitsFIFOcontains
X or less words and is HIGH when its FIFO contains (X+1) or more words. A
data word present in the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew
leveloffill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormore
wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
sincethewritethatfilledthememorytothe(X+1)level. AnAlmost-Emptyflag
issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter
theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionof
anAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycle
ifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)words.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figures 16 and 17).
ALMOST-FULL FLAGS (AFA, AFB)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsa
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
statusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstateisdefined
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| IDT72V3632L10PF8 | 功能描述:IC BIFIFO 512X36X2 10NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3632L10PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512X36X2 SYNC 120TQFP |
| IDT72V3632L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512X36X2 SYNC 120TQFP |
| IDT72V3632L10PQF | 功能描述:IC BIFIFO 512X36X2 10NS 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3632L15PF | 功能描述:IC BIFIFO 512X36X2 15NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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