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參數(shù)資料
| 型號： | IDT72V3631L20PQF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNCFIFO 512X36 20NS 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲容量： | 18.4K（512 x 36） |
| 數(shù)據(jù)速率： | 520Mbs |
| 訪問時間： | 20ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 供應(yīng)商設(shè)備封裝： | 132-PQFP（24.13x24.13） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3631L20PQF |
10
COMMERCIALTEMPERATURERANGE
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO 512 x 36, 1,024 x 36 and 2,048 x 36
SYNCHRONIZED FIFO FLAGS
Each IDT72V3631/72V3641/72V3651 FIFO flag is synchronized to its port
Clock through at least two flip-flop stages. This is done to improve the flags’
reliabilitybyreducingtheprobabilityofmetastableeventsontheiroutputswhen
CLKA and CLKB operate asynchronously to one another. OR and
AE are
synchronized to CLKB. IR and
AF aresynchronizedtoCLKA. Table4shows
the relationship of each flag to the number of words stored in memory.
OUTPUT READY FLAG (OR)
TheOutputReadyflagofaFIFOissynchronizedtotheportClockthatreads
data from its array (CLKB). When the OR flag is HIGH, new data is present
in the FIFO output register. When the OR flag is LOW, the previous data word
is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its
output register. The state machine that controls an OR flag monitors a write-
pointer and read-pointer comparator that indicates when the FIFO memory
statusisempty,empty+1,orempty+2. FromthetimeawordiswrittentoaFIFO,
itcanbeshiftedtotheFIFOoutputregisterinaminimumofthreecyclesofCLKB.
Therefore, an OR flag is LOW if a word in memory is the next data to be sent
to the FIFO output register and three CLKB cycles have not elapsed since the
time the word was written. The OR flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of CLKB occurs, simultaneously forcing the OR flag
HIGH and shifting the word to the FIFO output register.
ALOW-to-HIGHtransitiononCLKBbeginsthefirstsynchronizationcycleof
a write if the clock transition occurs at time tSKEW1 or greater after the write.
Otherwise, the subsequent CLKB cycle may be the first synchronization cycle
(see Figure 7).
INPUT READY FLAG (IR)
The Input Ready flag of a FIFO is synchronized to the port Clock that writes
data to its array (CLKA). When the IR flag is HIGH, a memory location is free
in the FIFO to write new data. No memory locations are free when the IR flag
is LOW and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. The
state machine that controls an IR flag monitors a write-pointer and read pointer
comparator that indicates when the FIFO memory status is full, full-1, or full-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
tobewritteninaminimumofthreecyclesofCLKA. Therefore,anIRflagisLOW
iflessthantwocyclesofCLKAhaveelapsedsincethenextmemorywritelocation
has been read. The second LOW-to-HIGH transition on CLKA after the read
sets the Input Ready flag HIGH, and data can be written in the following cycle.
ALOW-to-HIGHtransitiononCLKAbeginsthefirstsynchronizationcycleof
a read if the clock transition occurs at time tSKEW1 or greater after the read.
Otherwise, the subsequent CLKA cycle may be the first synchronization cycle
(see Figure 8).
ALMOST-EMPTY FLAG (
AE)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportClockthatreads
datafromitsarray(CLKB). Thestatemachinethatcontrolsan
AEflagmonitors
a write-pointer and read-pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX. Thisregisterisloaded
with a preset value during a FIFO reset, programmed from port A, or
programmed serially (see Almost-Empty flag and Almost-Full flag offset pro-
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-A35) I/O
Port Functions
H
X
Input
None
L
X
Input
None
LL
H
L
↑
Input
None
LL
H
↑
Input
Mail2 Write
L
H
L
X
Output
None
LH
HL
↑
Output
FIFO read
L
H
L
H
X
Output
None
L
HHH
↑
Output
Mail1 Read (Set
MBF1 HIGH)
CSA
W/
RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Functions
H
X
Input
None
L
H
L
X
Input
None
LH
HL
↑
Input
FIFO Write
LH
H
↑
Input
Mail1 Write
L
X
Output
None
LL
H
L
↑
Output
None
L
H
X
Output
None
LL
H
↑
Output
Mail2 Read (Set
MBF2 HIGH)
TABLE 2 —
—
— PORT-A ENABLE FUNCTION TABLE
TABLE 3 —
—
— PORT-B ENABLE FUNCTION TABLE
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