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參數(shù)資料
| 型號： | IDT72V3613L12PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO CLOCK 64X36 12NS 120TQFP |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 2.3K（64 x 36） |
| 數(shù)據(jù)速率： | 83MHz |
| 訪問時間： | 12ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3613L12PF |
11
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIALTEMPERATURERANGE
ThelevelsappliedtotheportBbus-sizeselect(SIZ0,SIZ1)inputsandthe
Big-Endianselect(BE)inputarestoredoneachCLKBLOW-to-HIGHtransition.
ThestoredportBbus-sizeselectionisimplementedbythenextrisingedgeon
CLKB according to Figure 2.
Only 36-bit long-word data is written to or read from the FIFO memory on
theIDT72V3613.Bus-matchingoperationsaredoneafterdataisreadfromthe
FIFO RAM. Port B bus sizing does not apply to mail register operations.
BUS-MATCHING FIFO READS
DataisreadfromtheFIFORAMin36-bitlong-wordincrements.Ifalong-
word bus-size is implemented, the entire long word immediately shifts to the
FIFO output register upon a read. If byte or word size is implemented on port
B, only the first one or two bytes appear on the selected portion of the FIFO
output register, with the rest of the long word stored in auxiliary registers. In
this case, subsequent FIFO reads with the same bus-size implementation
outputtherestofthelongwordtotheFIFOoutputregisterintheordershown
by Figure 2.
EachFIFOreadwithanewbus-sizeimplementationautomaticallyunloads
datafromtheFIFORAMtoitsoutputregisterandauxiliaryregisters.Therefore,
implementinganewportBbus-sizeandperformingaFIFOreadbeforeallbytes
orwordsstoredintheauxiliaryregistershavebeenreadresultsinalossofthe
unread data in these registers.
When reading data from FIFO in byte or word format, the unused B0-B35
outputsareindeterminate.
BYTE SWAPPING
The byte-order arrangement of data read from the FIFO can be changed
synchronoustotherisingedgeofCLKB.Byte-orderswappingisnotavailable
formailregisterdata.Fourmodesofbyte-orderswapping(includingnoswap)
can be done with any data port size selection. The order of the bytes are
rearranged within the long word, but the bit order within the bytes remains
constant.
BytearrangementischosenbytheportBSwapselect(SW0,SW1)inputs
on a CLKB rising edge that reads a new long word from the FIFO. The byte
orderchosenonthefirstbyteorfirstwordofanewlongwordreadfromtheFIFO
ismaintaineduntiltheentirelongwordistransferred,regardlessoftheSW0and
SW1statesduringsubsequentreads.Figure4isanexampleofthebyte-order
swappingavailableforlongwordreads.Performingabyteswapandbus-size
simultaneously for a FIFO read first rearranges the bytes as shown in Figure
4, then outputs the bytes as shown in Figure 2.
PORT-B MAIL REGISTER ACCESS
InadditiontoselectingportBbussizesforFIFOreads,theportBbusSize
select(SIZ0,SIZ1)inputsalsoaccessthemailregisters.WhenbothSIZ0and
SIZ1areHIGH,themail1registerisaccessedforaportBlong-wordreadand
themail2registerisaccessedforaportBlong-wordwrite.Themailregisteris
accessedimmediatelyandanybus-sizingoperationthatcanbeunderwayis
unaffectedbythemailregisteraccess.Afterthemailregisteraccessiscomplete,
thepreviousFIFOaccesscanresumeinthenextCLKBcycle.Thelogicdiagram
inFigure3showsthepreviousbus-sizeselectionispreservedwhenthemail
registersareaccessedfromportB.AportBbus-sizeisimplementedoneach
rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and BE_Q.
PARITY CHECKING
TheportAdatainputs(A0-A35) andportBdatainputs(B0-B35)eachhave
fourparitytreestochecktheparityofincoming(oroutgoing)data. Aparityfailure
on one or more bytes of the port A data bus is reported by a low level on the
port A Parity Error Flag (PEFA). A parity failure on one or more bytes of the
portBdatainputsthatarevalidforthebus-sizeimplementationisreportedby
alowlevelontheportBParityErrorFlag(PEFB).OddorEvenparitychecking
can be selected, and the Parity Error Flags can be ignored if this feature is not
desired.
ParitystatusischeckedoneachinputbusaccordingtotheleveloftheOdd/
Evenparity(ODD/EVEN)selectinput. Aparityerrorononeormorevalidbytes
ofaportisreportedbyaLOWlevelonthecorrespondingportParityErrorFlag
(PEFA,PEFB)output. PortAbytesarearrangedasA0-A8,A9-A17,A18-A26,
andA27-A35,andportBbytesarearrangedasB0-B8,B9-B17,B18-B26,and
B27-B35,anditsvalidbytesarethoseusedinaportBbussizeimplementation.
When Odd/Even parity is selected, a port Parity Error Flag (PEFA, PEFB) is
LOW if any byte on the port has an odd/even number of LOW levels applied
toitsbits.
The four parity trees used to check the A0-A35 inputs are shared by the
mail2registerwhenparitygenerationisselectedforport-Areads(PGA=HIGH).
WhenaportAreadfromthemail2registerwithparitygenerationisselectedwith
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A
Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the
A0-A35inputs. Likewise,theparitytreesusedtochecktheB0-B35inputsare
sharedbythemail1registerwhenparitygenerationisselectedforportBreads
(PGB=HIGH). WhenaportBreadfromthemail1registerwithparitygeneration
isselectedwithCSBLOW,ENBHIGH,W/RBLOW,bothSIZ0andSIZ1HIGH,
and PGB HIGH, the port B Parity Error Flag (PEFB) is held HIGH regardless
of the levels applied to the B0-B35 inputs.
PARITYGENERATION
A HIGH level on the port A Parity Generate select (PGA) or port B Parity
Generateselect(PGB)enablestheIDT72V3613togenerateparitybitsforport
reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8,
A9-A17,A18-A26,andA27-A35,withthemostsignificantbitofeachbyteused
as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35,withthemostsignificantbitofeachbyteusedastheparitybit. Awrite
to a FIFO or mail register stores the levels applied to all nine inputs of a byte
regardlessofthestateoftheParityGenerateselect(PGA,PGB)inputs.When
dataisreadfromaportwithparitygenerationselected,thelowereightbitsof
eachbyteareusedtogenerateaparitybitaccordingtothelevelontheODD/
EVENselect. Thegeneratedparitybitsaresubstitutedforthelevelsoriginally
written to the most significant bits of each byte as the word is read to the data
outputs.
ParitybitsforFIFOdataaregeneratedafterthedataisreadfromtheFIFO
memoryandbeforethedataiswrittentotheoutputregister. Therefore,theport
AParityGenerateselect(PGA)andOdd/Evenparityselect(ODD/EVEN)have
setupandholdtimeconstraintstotheportAClock(CLKA)andtheportBParity
Generate select (PGB) and ODD/EVEN select have setup and hold time
constraintstotheportBClock(CLKB).Thesetimingconstraintsonlyapplyfor
a rising clock edge used to read a new long word to the FIFO output register
(see Figure 16 and 17).
Thecircuitusedtogenerateparityforthemail1dataissharedbytheport
B bus (B0-B35) to check parity and the circuit used to generate parity for the
mail2 data is shared by the port A bus (A0-A35) to check parity. The shared
paritytreesofaportareusedtogenerateparitybitsforthedatainamailregister
when the port Chip Select (CSA, CSB)isLOW,Enable(ENA, ENB) is HIGH,
andWrite/Readselect(W/RA,W/RB)inputisLOW,themailregisterisselected
(MBAHIGHforportA;bothSIZ0andSIZ1areHIGHforportB),andportParity
Generateselect(PGA,PGB)isHIGH. Generatingparityformailregisterdata
doesnotchangethecontentsoftheregister. ParityGenerationtiming,when
reading from a mail register, can be found in Figure 18 and 19.
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| IDT72V3613L12PF8 | 功能描述:IC FIFO CLOCK 64X36 12NS 120TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3613L12PQF | 功能描述:IC FIFO CLOCK 64X36 12NS 132PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3613L15PF | 功能描述:IC FIFO CLOCK 64X36 15NS 120TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3613L15PF8 | 功能描述:IC FIFO CLOCK 64X36 15NS 120TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3613L15PQF | 功能描述:IC FIFO CLOCK 64X36 15NS 132PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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