IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72V36110L7-5BB8
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 48/48闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FIFO 131KX36 7-5NS 144BGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
绯诲垪锛� 72V
鍔熻兘锛� 鍚屾
瀛樺劜瀹归噺锛� 4.7M锛�131K x 36锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 166MHz
瑷晱鏅傞枔锛� 5ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 144-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-PBGA锛�13x13锛�
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� 72V36110L7-5BB8
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V 卤 0.15V, TA = 0
掳C to +70掳C; Industrial: VCC = 3.3V 卤 0.15V, TA = -40掳C to +85掳C; JEDEC JESD8-A compliant)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 7-5ns and 15ns are available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7-5ns, 10ns and 15ns the minimum for tA, tOE, and tOHZ is 2ns.
Commercial
Com鈥檒 & Ind鈥檒(2)
Commercial
Com鈥檒 & Ind鈥檒(2)
PBGA & TQFP
TQFP Only
IDT72V36100L6
IDT72V36100L7-5
IDT72V36100L10
IDT72V36100L15
IDT72V36110L6
IDT72V36110L7-5
IDT72V36110L10
IDT72V36110L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
鈥�
166
鈥�
133.3
鈥�
100
鈥�
66.7
MHz
tA
Data Access Time(5)
14
1(5)
51(5)
6.5
1(5)
10
ns
tCLK
Clock Cycle Time
6
鈥�
7.5
鈥�
10
鈥�
15
鈥�
ns
tCLKH
Clock High Time
2.7
鈥�
3.5
鈥�
4.5
鈥�
6
鈥�
ns
tCLKL
Clock Low Time
2.7
鈥�
3.5
鈥�
4.5
鈥�
6
鈥�
ns
tDS
DataSetupTime
2
鈥�
2.5
鈥�
3.5
鈥�
4
鈥�
ns
tDH
Data Hold Time
0.5
鈥�
0.5
鈥�
0.5
鈥�
1
鈥�
ns
tENS
Enable Setup Time
2
鈥�
2.5
鈥�
3.5
鈥�
4
鈥�
ns
tENH
Enable Hold Time
0.5
鈥�
0.5
鈥�
0.5
鈥�
1
鈥�
ns
tLDS
LoadSetupTime
3
鈥�
3.5
鈥�
3.5
鈥�
4
鈥�
ns
tLDH
Load Hold Time
0.5
鈥�
0.5
鈥�
0.5
鈥�
1
鈥�
ns
tRS
Reset Pulse Width(3)
10
鈥�
10
鈥�
10
鈥�
15
鈥�
ns
tRSS
ResetSetupTime
15
鈥�
15
鈥�
15
鈥�
15
鈥�
ns
tRSR
Reset Recovery Time
10
鈥�
10
鈥�
10
鈥�
15
鈥�
ns
tRSF
Reset to Flag and Output Time
鈥�
15
鈥�
15
鈥�
15
鈥�
15
ns
tRTS
RetransmitSetupTime
3
鈥�
3.5
鈥�
3.5
鈥�
4
鈥�
ns
tOLZ
Output Enable to Output in Low Z(4)
0鈥�
0
鈥�
0鈥�
ns
tOE
Output Enable to Output Valid(5)
14
1(5)
61(5)
8ns
tOHZ
Output Enable to Output in High Z(4,5)
14
1(5)
61(5)
8ns
tWFF
Write Clock to
FF or IR
鈥�4
鈥�5
鈥�6.5
鈥�
10
ns
tREF
Read Clock to
EF or OR
鈥�4
鈥�5
鈥�6.5
鈥�
10
ns
tPAFA
Clock to Asynchronous Programmable Almost-Full Flag
鈥�
10
鈥�
12.5
鈥�
16
鈥�
20
ns
tPAFS
Write Clock to Synchronous Programmable Almost-Full Flag
鈥�
4
鈥�
5
鈥�
6.5
鈥�
10
ns
tPAEA
Clock to Asynchronous Programmable Almost-Empty Flag
鈥�
10
鈥�
12.5
鈥�
16
鈥�
20
ns
tPAES
Read Clock to Synchronous Programmable Almost-Empty Flag
鈥�
4
鈥�
5
鈥�
6.5
鈥�
10
ns
tHF
Clock to
HF
鈥�
10
鈥�
12.5
鈥�
16
鈥�
20
ns
tSKEW1
Skew time between RCLK and WCLK for
EF/OR and FF/IR
4鈥�
5鈥�
7
鈥�
9鈥�
ns
tSKEW2
Skew time between RCLK and WCLK for
PAE and PAF
5鈥�
7鈥�
10
鈥�
14
鈥�
ns
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