SUPERSYNC FIFOTM
參數(shù)資料
型號(hào)： IDT72V295L20PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 6/26頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SUPERSYNCII 20NS 64-TQFP
標(biāo)準(zhǔn)包裝： 750
系列： 72V
功能： 同步
存儲(chǔ)容量： 2.3K（64 x 36）
訪問(wèn)時(shí)間： 20ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 72V295L20PF8
14
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EFis a double register-buffered output. In FWFT
mode,
OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF )
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The
PAF will go LOW after (131,072-m) writes for the IDT72V295
and (262,144-m) writes for the IDT72V2105. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAF will go LOW after (131,073-m) writes for the
IDT72V295 and (262,145-m) writes for the IDT72V2105, where m is the full
offset value. The default setting for this value is stated in the footnote of
Table 2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE )
The Programmable Almost-Empty flag (
PAE) will go LOW when the
FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will
go LOW when there are n words or less in the FIFO. The offset “n” is the empty
offset value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in the footnote of Table 2.
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Stan-
dard and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (
HF )
This output indicates a half-full FIFO. The rising WCLK edge that fills the
FIFO beyond half-full sets
HF LOW. The flag remains LOW until the
difference between the write and read pointers becomes less than or equal
to half of the total depth of the device; the rising RCLK edge that accom-
plishes this condition sets
HF HIGH.
In IDT Standard mode, if no reads are performed after reset (
MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 131,072
for the IDT72V295 and 262,144 for the IDT72V2105.
In FWFT mode, if no reads are performed after reset (
MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 131,073 for the
IDT72V295 and 262,145 for the IDT72V2105.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because
HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS ( Q0-Q17 )
(Q0 - Q17) are data outputs for 18-bit wide data.
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