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參數(shù)資料
| 型號： | IDT72V295L15PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SUPERSYNCII 15NS 64-TQFP |
| 標準包裝： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 2.3K（64 x 36） |
| 訪問時間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 72V295L15PF |
1
OCTOBER 2008
3.3 VOLT HIGH DENSITY CMOS
SUPERSYNC FIFO
131,072 x 18
262,144 x 18
IDT72V295
IDT72V2105
DSC-4668/4
2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
Choose among the following memory organizations:
IDT72V295
131,072 x 18
IDT72V2105
262,144 x 18
Pin-compatible with the IDT72V255/72V265 and the IDT72V275/
72V285 SuperSync FIFOs
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
5V input tolerant
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using
OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP)
High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
131,072 x 18
262,144 x 18
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK
D0 -D17
LD
MRS
REN
RCLK
OE
Q0 -Q17
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
4668 drw 01
DESCRIPTION:
The IDT72V295/72V2105 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls. These
FIFOs offer numerous improvements over previous SuperSync FIFOs, includ-
ing the following:
The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V295L15PF8 | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V295L15PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP |
| IDT72V295L15PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP |
| IDT72V295L15PFI | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V295L15PFI8 | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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