IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
參數(shù)資料
型號(hào)： IDT72V293L10PFI8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 5/45頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 65536X18 10NS 80QFP
標(biāo)準(zhǔn)包裝： 750
系列： 72V
功能： 同步
存儲(chǔ)容量： 1.1M（65K x 18）
數(shù)據(jù)速率： 166MHz
訪問(wèn)時(shí)間： 10ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱(chēng)： 72V293L10PFI8
13
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
TABLE 2 DEFAULT PROGRAMMABLE FLAG OFFSETS
IDT72V253
IDT72V223
IDT72V263
IDT72V233
IDT72V243
IDT72V273
IDT72V283
IDT72V293
Offsets n,m
All Other
x9 to x9
All Other
x9 to x9
LD
FSEL0
FSEL1
All Modes
Modes
Mode
All Modes
Modes
Mode
All Modes
L
H
511
16,383
L
H
L
255
8,191
L
H
63
4,095
H
L
H
15
31
2,047
H
L
31
1,023
H
L
7
15
511
H
3
7
255
L
127
H
X
Serial Programming Mode(3)
L
X
Parallel Programming Mode(4)
(32,769-m) writes for the IDT72V273, (65,537-m) writes for the IDT72V283
and (131,073-m) writes for the IDT72V293. The offset m is the full offset value.
The default setting for these values are stated in the footnote of Table 2.
WhentheFIFOisfull,theInputReady(
IR)flagwillgoHIGH,inhibitingfurther
write operations. If no reads are performed after a reset,
IR will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 513
writes for the IDT72V223, 1,025 writes for the IDT72V233, 2,049 writes for the
IDT72V243, 4,097 writes for the IDT72V253, 8,193 writes for the IDT72V263,
16,385 writes for the IDT72V273, 32,769 writes for the IDT72V283 and 65,537
writesfortheIDT72V293.Ifbothx9Inputandx9OutputbusWidthsareselected,
D = 1,025 writes for the IDT72V223, 2,049 writes for the IDT72V233, 4,097
writes for the IDT72V243, 8,193 writes for the IDT72V253, 16,385 writes for
the IDT72V263, 32,769 writes for the IDT72V273, 65,537 writes for the
IDT72V283 and 131,073 writes for the IDT72V293, respectively. Note that the
additionalwordinFWFTmodeisduetothecapacityofthememoryplusoutput
register.
If the FIFO is full, the first read operation will cause the
IR flag to go LOW.
Subsequent read operations will cause the
PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the
PAEwillgoLOWwhentherearen+1wordsintheFIFO,where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO,
OR will go
HIGHinhibitingfurtherreadoperations.
RENisignoredwhentheFIFOisempty.
When configured in FWFT mode, the
OR flag output is triple register-
buffered, and the
IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and
12.
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V223/
72V233/72V243/72V253/72V263/72V273/72V283/72V293 has internalreg-
isters for these offsets. There are eight default offset values selectable during
MasterReset.TheseoffsetvaluesareshowninTable2.Offsetvaluescanalso
be programmed into the FIFO in one of two ways; serial or parallel loading
method. The selection of the loading method is done using the
LD (Load)pin.
During Master Reset, the state of the
LD input determines whether serial or
parallelflagoffsetprogrammingisenabled.AHIGHon
LDduringMasterReset
selectsserialloadingofoffsetvalues.ALOWon
LDduringMasterResetselects
parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
For a more detailed description, see discussion that follows.
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 can be configured during the Master Reset cycle with either synchro-
nous or asynchronous timing for
PAF and PAE flags by use of the PFM pin.
If synchronous
PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly,
PAEisassertedandupdatedontherisingedgeofRCLK
only and not WCLK. For detail timing diagrams, see Figure 18 for synchronous
PAF timing and Figure 19 for synchronous PAE timing.
If asynchronous
PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK.Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure
20 for asynchronous
PAFtimingandFigure21forasynchronousPAEtiming.
NOTES:
1. n = empty offset for
PAE.
2. m = full offset for
PAF.
3. As well as selecting serial programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.
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