IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM 65,536 x 9 " />
參數(shù)資料
型號: IDT72V291L20PF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 6/26頁
文件大?。?/td> 0K
描述: IC FIFO SS 32768X36 20NS 64QFP
標(biāo)準(zhǔn)包裝: 90
系列: 72V
功能: 同步
存儲容量: 1.1M(32K x 36)
數(shù)據(jù)速率: 50MHz
訪問時間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 托盤
其它名稱: 72V291L20PF
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM
65,536 x 9 and 131,072 x 9
PROGRAMMABLE ALMOST-FULL FLAG (
PAF
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAF will go LOW after (D - m) words are
written to the FIFO. The
PAF will go LOW after (65,536-m) writes for the
IDT72V281 and (131,072-m) writes for the IDT72V291. The offset “m” is the
full offset value. The default setting for this value is stated in the footnote of
Table 1.
In FWFT mode, the
PAF will go LOW after (65,537-m) writes for the
IDT72V281 and (131,073-m) writes for the IDT72V291, where m is the full
offset value. The default setting for this value is stated in the footnote of
Table 2.
See Figure 18, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE
PAE)
The Programmable Almost-Empty flag (
PAE) will go LOW when the
FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will
go LOW when there are n words or less in the FIFO. The offset “n” is the
empty offset value. The default setting for this value is stated in the footnote
of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less in
the FIFO. The default setting for this value is stated in the footnote of Table 2.
See Figure 19, Programmable Almost-Empty Flag Timing (IDT Stan-
dard and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (
HF
HF)
This output indicates a half-full FIFO. The rising WCLK edge that fills the
FIFO beyond half-full sets
HF LOW. The flag remains LOW until the
difference between the write and read pointers becomes less than or equal
to half of the total depth of the device; the rising RCLK edge that accom-
plishes this condition sets
HF HIGH.
In IDT Standard mode, if no reads are performed after reset (
MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536
for the IDT72V281 and 131,072 for the IDT72V291.
In FWFT mode, if no reads are performed after reset (
MRS or PRS),
HF will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for
the IDT72V281 and 131,073 for the IDT72V291.
See Figure 20, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because
HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Q8)
(Q0 - Q8) are data outputs for 9-bit wide data.
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