參數(shù)資料
型號(hào): IDT72V261LA15PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 16/27頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SS 8192X18 15NS 64QFP
標(biāo)準(zhǔn)包裝: 90
系列: 72V
功能: 同步
存儲(chǔ)容量: 144K(8K x 18)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 托盤(pán)
其它名稱: 72V261LA15PF
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 and 32,768 x 9
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 30, 2009
WCLK
t ENH
t CLKH
tCLKL
WEN
PAF
RCLK
(3)
REN
4673 drw 19
t ENS
t ENH
t ENS
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
tSKEW2
1
2
12
D-(m+1) words
in FIFO(2)
tPAF
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t ENH
t CLKH
tCLKL
WEN
PAE
RCLK
t ENS
tPAE
tSKEW2
tPAE
12
(4)
REN
4673 drw 20
t ENS
t ENH
n+1 words in FIFO (2),
n+2 words in FIFO (3)
n words in FIFO (2),
n+1 words in FIFO (3)
n words in FIFO (2),
n+1 words in FIFO (3)
WCLK
tENS
tENH
WEN
HF
tENS
RCLK
REN
4673 drw 21
D/2 words in FIFO(1),
[
+ 1
] words in FIFO(2)
D-1
2
D/2 + 1 words in FIFO
(1),
[
+ 2
] words in FIFO(2)
D-1
2
D/2 words in FIFO(1),
[
+ 1
] words in FIFO(2)
D-1
2
tCLKH
tCLKL
tHF
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.
2. For FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.
NOTES:
1. n =
PAE offset.
2. For IDT Standard mode.
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the
PAE deassertion may be delayed one extra RCLK cycle.
5.
PAE is asserted and updated on the rising edge of WCLK only.
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.
In FWFT mode: D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the
PAF deassertion time may be delayed one extra WCLK cycle.
4.
PAF is asserted and updated on the rising edge of WCLK only.
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