參數(shù)資料
型號: IDT72V255LA20TF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/27頁
文件大?。?/td> 0K
描述: IC FIFO SS 8192X18 20NS 64-STQFP
標(biāo)準(zhǔn)包裝: 80
系列: 72V
功能: 同步
存儲容量: 144K(8K x 18)
訪問時間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 72V255LA20TF
11
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting
OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When
OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on
REN is
necessary. Reading all subsequent words requires a LOW on
REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
For either IDT Standard mode or FWFT mode, updating of the
PAE, HF
and
PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after
RT is
setup, the
PAE flag will be updated. HF is asynchronous, thus the rising
edge of RCLK that
RT is setup will update HF. PAF is synchronized to
WCLK, thus the second rising edge of WCLK that occurs tSKEW after the
rising edge of RCLK that
RT is setup will update PAF. RT is synchronized to
RCLK.
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