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參數(shù)資料
| 型號： | IDT72V2113L10PFI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 42/46頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO SUPERSYNCII 10NS 80-TQFP |
| 標準包裝： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 4.7Mb（262k x 18） |
| 訪問時間： | 10ns |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V2113L10PFI8 |
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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
to-HIGH transition of WCLK. Similarly, the
PAFisassertedLOWontheLOW-
to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
Ifsynchronous
PAE/PAFconfigurationisselected,thePAEisassertedand
updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF is
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringmasterresetbythestateoftheProgrammableFlag
Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the
RT inputduringarisingRCLKedgeinitiatesaretransmit
operation by setting the read pointer to the first location of the memory array.
A zero-latency retransmit timing mode can be selected using the Retransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero-
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero-latency retransmit operation is selected the first data word to be
retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK
edge that initiated the retransmit based on RT being LOW.
Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer
to Figure 13 and 14 for Retransmit Timing with zero-latency.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x18) and read
out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
IW
OW
Write Port Width
Read Port Width
L
x18
L
H
x18
x9
H
L
x9
x18
H
x9
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (
BE) pin.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFOwillassumethattheparitybitislocatedinbitpositionD8 duringtheparallel
programmingoftheflagoffsets.IfNon-InterspersedParitymodeisselected,then
D8isassumedtobeavalidbitandD16 andD17 areignored.IPmodeisselected
during Master Reset by the state of the IP input pin. This mode is relevant only
when the input width is set to x18 mode. Interspersed Parity control only has
aneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthe
data written to and read from the FIFO.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized.Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72V2103/72V2113 are fabricated using IDT’s high speed submi-
cron CMOS technology.
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| IDT72V2113L15PF | 功能描述:IC FIFO SUPERSYNCII 15NS 80-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V2113L15PF8 | 功能描述:IC FIFO SUPERSYNCII 15NS 80-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V2113L6BC | 功能描述:IC FIFO SUPERSYNCII 6NS 100-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V2113L6PF | 功能描述:IC FIFO SUPERSYNCII 6NS 80-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V2113L6PF8 | 功能描述:IC FIFO SUPERSYNCII 6NS 80-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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