IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
參數(shù)資料
型號(hào): IDT72V2103L7-5BCI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 8/46頁(yè)
文件大小: 0K
描述: IC FIFO SUPERSYNCII 7-5NS 100BGA
標(biāo)準(zhǔn)包裝: 1
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 2.3K(131 x 18)
數(shù)據(jù)速率: 133MHz
訪問(wèn)時(shí)間: 5ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-CABGA(11x11)
包裝: 托盤
其它名稱: 72V2103L7-5BCI
16
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
WCLK
RCLK
X
XX
X
XX
LD
0
X
1
0
WEN
0
1
0
X
1
REN
1
0
1
X
0
1
1X
SEN
1
X
0
No Operation
Write Memory
Read Memory
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
Ending with Full Offset (MSB)
IDT72V2103
IDT72V2113
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
36 bits for the IDT72V2103
38 bits for the IDT72V2113
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Serial shift into registers:
Ending with Full Offset (MSB)
34 bits for the IDT72V2103
36 bits for the IDT72V2113
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
x9 to x9 Mode
All Other Modes
6119 drw06b
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
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