IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
參數(shù)資料
型號(hào): IDT72V2103L10PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 28/46頁
文件大?。?/td> 0K
描述: IC FIFO SUPERSYNCII 10NS 80-TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 2.3K(131 x 18)
數(shù)據(jù)速率: 100MHz
訪問時(shí)間: 10ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V2103L10PF8
34
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
NOTES:
1. n =
PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the
PAE deassertion may be delayed one extra RCLK cycle.
5.
PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
WCLK
tENH
WEN
PAE
RCLK
tENS
n words in FIFO
(2),
n+1 words in FIFO (3)
tPAES
tSKEW2(4)
tPAES
12
REN
6119 drw22
tENS
tENH
n+1 words in FIFO
(2),
n+2 words in FIFO (3)
n words in FIFO
(2),
n+1 words in FIFO(3)
tCLKL
tCLKH
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths
are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the DT72V2113. If both x9 Input and x9 Output bus Widths are
selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
3.
PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
WCLK
tCLKH
tENS
tENH
WEN
PAF
tENS
D
(m + 1)
words in FIFO
RCLK
REN
6119 drw23
D
m words
in FIFO
D
(m + 1) words in FIFO
tCLKL
tPAFA
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
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