參數(shù)資料
型號(hào)： IDT72T7295L4-4BB
廠(chǎng)商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 11/53頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 32768X72 4-4NS 324-BGA
標(biāo)準(zhǔn)包裝： 1
系列： 72T
訪(fǎng)問(wèn)時(shí)間： 3.2ns
電源電壓： 2.375 V ~ 2.625 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 324-BGA
供應(yīng)商設(shè)備封裝： 324-PBGA（19x19）
包裝： 托盤(pán)
其它名稱(chēng)： 72T7295L4-4BB
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of
PAEandPAFvaluescanbeachievedbyusingacombination
of the
LD,SEN,SCLKandSIinputpins.ProgrammingPAEandPAFproceeds
asfollows:when
LDandSENaresetLOW,dataontheSIinputarewritten,one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. A total of 28 bits for the IDT72T7285, 30 bits for the
IDT72T7295, 32 bits for the IDT72T72105 and 34 bits for the IDT72T72115.
See Figure 20, Serial Loading of Programmable Flag Registers, for the timing
diagram for this mode.
Using the serial method, individual registers cannot be programmed selec-
tively.
PAEand PAFcanshowavalidstatusonlyafterthecompletesetofbits
(for all offset registers) has been entered. The registers can be reprogrammed
as long as the complete set of new offset bits is entered. When
LDisLOWand
SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing
LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling
WEN. WhenWEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruptionofserialprogrammingisdesired,itissufficienteithertoset
LDLOW
and deactivate
SENortosetSENLOWanddeactivateLD. OnceLDandSEN
are both restored to a LOW level, serial offset programming continues.
Fromthetimeserialprogramminghasbegun,neitherprogrammableflagwill
bevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeenwritten.
MeasuringfromtherisingSCLKedgethatachievestheabovecriteria;
PAFwill
be valid after three more rising WCLK edges plus tPAF,
PAE will be valid after
the next three rising RCLK edges plus tPAE.
It is only possible to read the flag offset values via the parallel output port Qn.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, then
programming of
PAEandPAFvaluescanbeachievedbyusingacombination
of the
LD, WCLK , WEN and Dn input pins. Programming PAE and PAF
proceeds as follows:
LDandWENmustbesetLOW.Forx72,x36orx18data
on the inputs Dn are written into the Empty Offset Register on the first LOW-to-
HIGHtransitionofWCLK.UponthesecondLOW-to-HIGHtransitionofWCLK,
dataarewrittenintotheFullOffsetRegister.ThethirdtransitionofWCLKwrites,
once again, to the Empty Offset Register. See Figure 3, Programmable Flag
Offset Programming Sequence. See Figure 21, Parallel Loading of Program-
mable Flag Registers, for the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset register
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
not have to occur at one time. One, two or more offset registers can be written
and then by bringing
LDHIGH,writeoperationscanberedirectedtotheFIFO
memory. When
LDissetLOWagain,andWENisLOW,thenextoffsetregister
in sequence is written to. As an alternative to holding
WENLOWandtoggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling
WEN.
Note that the status of a programmable flag (
PAE or PAF) output is invalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria;
PAF will be valid after
twomorerisingWCLKedgesplustPAF,
PAEwillbevalidafterthenexttworising
RCLK edges plus tPAE plus tSKEW2.
Theactofreadingtheoffsetregistersemploysadedicatedreadoffsetregister
pointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Qnpinswhen
LDissetLOWandRENissetLOW.Itisimportanttonotethatconsecutivereads
of the offset registers is not permitted. The read operation must be disabled for
aminimumofoneRCLKcycleinbetweenoffsetregisteraccesses.Forx72,x36
and x18 output bus width, 2 read cycles are required to obtain the values of the
offsetregisters.StartingwiththeEmptyOffsetRegistersLSBandfinishingwith
the Full Offset Registers MSB. See Figure 3, Programmable Flag Offset
Programming Sequence. See Figure 22, Parallel Read of Programmable
Flag Registers, for the timing diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting
REN,LD,
or both together. When
REN and LD are restored to a LOW level, reading of
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallelreadingoftheoffsetregistersisalwayspermittedregardlessofwhich
timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT FROM MARK OPERATION
The Retransmit from Mark feature allows FIFO data to be read repeatedly
startingatauser-selectedposition.TheFIFOisfirstputintoretransmitmodethat
will‘mark’abeginningwordandalsosetapointerthatwillpreventongoingFIFO
write operations from over-writing retransmit data. The retransmit data can be
read repeatedly any number of times from the ‘marked’ position. The FIFO can
be taken out of retransmit mode at any time to allow normal device operation.
The ‘mark’ position can be selected any number of times, each selection over-
writingthepreviousmarklocation.RetransmitoperationisavailableinbothIDT
standard and FWFT modes.
During IDT standard mode the FIFO is put into retransmit mode by a Low-
to-High transition on RCLK when the ‘MARK’ input is HIGH and
EF is HIGH.
The rising RCLK edge ‘marks’ the data present in the FIFO output register as
thefirstretransmitdata.TheFIFOremainsinretransmitmodeuntilarisingedge
on RCLK occurs while MARK is LOW.
Once a ‘marked’ location has been set (and the device is still in retransmit
mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK
while the retransmit input (
RT) is LOW. REN must be HIGH (reads disabled)
before bringing
RTLOW.Thedeviceindicatesthestartofretransmitsetupby
setting
EFLOW,alsopreventingreads.WhenEFgoesHIGH,retransmitsetup
iscompleteandreadoperationsmaybeginstartingwiththefirstdataattheMARK
location. Since IDT standard mode is selected, every word read including the
first ‘marked’ word following a retransmit setup requires a LOW on
REN(read
enabled).
Note,writeoperationsmaycontinueasnormalduringallretransmitfunctions,
howeverwriteoperationstothe‘marked’locationwillbeprevented.SeeFigure
18, Retransmit from Mark (IDT standard mode), for the relevant timing
diagram.
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
edge when the ‘MARK’ input is HIGH and
OR is LOW. The rising RCLK edge
‘marks’ the data present in the FIFO output register as the first retransmit data.
The FIFO remains in retransmit mode until a rising RCLK edge occurs while
MARK is LOW.
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