參數(shù)資料
型號: IDT72T7285L5BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 47/53頁
文件大小: 0K
描述: IC FIFO 16384X72 5NS 324-BGA
標準包裝: 1
系列: 72T
訪問時間: 5ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 324-BGA
供應商設備封裝: 324-PBGA(19x19)
包裝: 托盤
其它名稱: 72T7285L5BB
51
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the
EFandFF functionsinIDTStandardmodeandtheIR
and
ORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
and WCLK, it is possible for
EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing
EF of every FIFO, and
separately ANDing
FF of every FIFO. In FWFT mode, composite flags can
be created by ORing
OR of every FIFO, and separately ORing IR of every
FIFO.
Figure 36 demonstrates a width expansion using two IDT72T7285/
72T7295/72T72105/72T72115 devices. D0 - D71 from each device form a
144-bitwideinputbusandQ0-Q71fromeachdeviceforma144-bitwideoutput
bus. Any word width can be attained by adding additional IDT72T7285/
72T7295/72T72105/72T72115 devices.
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of 16,384 x 144, 32,768 x 144, 65,536 x 144 and 131,072 x 144 Width Expansion
WRITE CLOCK (WCLK)
m + n
mn
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72T7285
72T7295
72T72105
72T72115
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PARTIAL RESET (PRS)
5994 drw41
FULL FLAG/INPUT READY (FF/IR) #2
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
READ CHIP SELECT (RCS)
SERIAL CLOCK (SCLK)
IDT
72T7285
72T7295
72T72105
72T72115
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