參數(shù)資料
型號(hào): IDT72T3645L4-4BB
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 21/57頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 1024X36 4-4NS 208-BGA
標(biāo)準(zhǔn)包裝: 1
系列: 72T
功能: 異步,同步
存儲(chǔ)容量: 36.8K(1K x 36)
數(shù)據(jù)速率: 100MHz
訪問(wèn)時(shí)間: 3.4ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-BGA
供應(yīng)商設(shè)備封裝: 208-PBGA(17x17)
包裝: 托盤
其它名稱: 72T3645L4-4BB
28
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
ECHO READ CLOCK (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
selectable via RHSTL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of
REN and RCS.
The ERCLK output follows the RCLK input with an associated delay. This
delay provides the user with a more effective read clock source when reading
data from the Qn outputs. This is especially helpful at high speeds when
variableswithinthedevicemaycausechangesinthedataaccesstimes. These
variations in access time maybe caused by ambient temperature, supply
voltage, device characteristics. The ERCLK output also compensates for any
tracelengthdelaysbetweentheQndataoutputsandreceivingdevicesinputs.
Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding
effectontheERCLKoutputproducedbytheFIFOdevice,thereforetheERCLK
outputleveltransitionsshouldalwaysbeatthesamepositionintimerelativeto
the data outputs. Note, that ERCLK is guaranteed by design to be slower than
the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data
Output Relationship, Figure 28, Echo Read Clock & Read Enable Operation
and Figure 29, Echo RCLK & Echo
REN Operation for timing information.
ECHO READ ENABLE (
EREN)
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
selectable via RHSTL.
The
EREN output is provided to be used in conjunction with the ERCLK
outputandprovidesthereadingdevicewithamoreeffectiveschemeforreading
data from the Qn output port at high speeds. The
ERENoutputiscontrolledby
internal logic that behaves as follows: The
ERENoutputisactiveLOWforthe
RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of
RCLKwillcause
ERENtogoactive,LOWifbothRENandRCSareactive,LOW
and the FIFO is NOT empty.
SERIAL CLOCK (SCLK)
Duringserialloadingoftheprogrammingflagoffsetregisters,arisingedge
on the SCLK input is used to load serial data present on the SI input provided
that the
SENinputisLOW.
DATA OUTPUTS (Q0-Qn)
(Q0-Q35) are data outputs for 36-bit wide data, (Q0 - Q17) are data outputs
for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.
Figure 4. Echo Read Clock and Data Output Relationship
NOTES:
1.
REN is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
5907 drw08
ERCLK
tA
tD
QSLOWEST(3)
RCLK
tERCLK
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