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參數(shù)資料
| 型號： | IDT72T36135ML6BBGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V 18M-BIT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS 524,288 x 36 |
| 中文描述： | 512K X 36 OTHER FIFO, 3.8 ns, PBGA240 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-240 |
| 文件頁數(shù)： | 1/48頁 |
| 文件大?。?/td> | 502K |
| 代理商： | IDT72T36135ML6BBGI |
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1
MAY 2006
DSC-6723/3
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
2.5V 18M-BIT HIGH-SPEED TeraSync
TM
FIFO 36-BIT CONFIGURATIONS
524,288 x 36
IDT72T36135M
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
Industry’s largest FIFO memory organization:
IDT72T36135
Up to 200 MHz Operation of Clocks
Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync
devices
User selectable HSTL/LVTTL Input and/or Output
User selectable Asynchronous read and/or write port timing
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (
WCS
) input disables Write Port
Read Chip Select (
RCS
) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
524,288 x 36 - 18M-bits
Separate SCLK input for Serial programming of flag offsets
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty and Full flags signal FIFO status
Select IDT Standard timing (using
EF[1:2]
and
FF[1:2]
flags) or First
Word Fall Through timing (using
OR[1:2]
and
IR[1:2]
flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
50% more space saving than the leading 9M-bit FIFOs
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40
°
C to +85
°
C) is available
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
524,288 x 36
FLAG
LOGIC
FF
/
IR[1:2]
PAF[1:2]
EF
/
OR[1:2]
PAE[1:2]
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK/WR
D
0
-D
n
(x36)
LD
MRS
REN
RCLK/RD
OE
Q
0
-Q
n
(x36)
OFFSET REGISTER
PRS
FWFT/SI
PFM
FSEL0
FSEL1
SEN
RT
MARK
ASYR
6723 drw01
SCLK
RCS
JTAG CONTROL
(BOUNDARY
SCAN)
TCK
TRST
TMS
TDO
TDI
WCS
HSTL I/0
CONTROL
Vref
WHSTL
RHSTL
SHSTL
ASYW
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T36135ML6BBI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512KX36 ASYNC 240BGA |
| IDT72T3645L4-4BB | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72T3645L4-4BBG | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72T3645L5BB | 功能描述:IC FIFO 1024X36 5NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72T3645L5BBI | 功能描述:IC FIFO 1024X36 5NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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