參數(shù)資料
型號(hào)： IDT72T36125L6BBI
廠商： Integrated Device Technology, Inc.
英文描述： 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
中文描述： 2.5伏高速TeraSyncTM FIFO的36位配置
文件頁(yè)數(shù)： 28/57頁(yè)
文件大小： 556K
代理商： IDT72T36125L6BBI
28
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
ECHO READ CLOCK (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
selectable via RHSTL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of
REN
and
RCS
.
The ERCLK output follows the RCLK input with an associated delay. This
delay provides the user with a more effective read clock source when reading
data fromthe Qn outputs. This is especially helpful at high speeds when
variables within the device may cause changes in the data access times. These
variations in access time maybe caused by ambient temperature, supply
voltage, device characteristics. The ERCLK output also compensates for any
trace length delays between the Qn data outputs and receiving devices inputs.
Any variations effecting the data access time will also have a corresponding
effect on the ERCLK output produced by the FIFO device, therefore the ERCLK
output level transitions should always be at the same position in time relative to
the data outputs. Note, that ERCLK is guaranteed by design to be slower than
the slowest Qn, data output. Refer to Figure 4,
Echo Read Clock and Data
Output Relationship
, Figure 28,
Echo Read Clock & Read Enable Operation
and Figure 29,
Echo RCLK & Echo
REN
Operation
for timng information.
ECHO READ ENABLE (
EREN
)
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
selectable via RHSTL.
The
EREN
output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for reading
data fromthe Qn output port at high speeds. The
EREN
output is controlled by
internal logic that behaves as follows: The
EREN
output is active LOW for the
RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of
RCLK will cause
EREN
to go active, LOW if both
REN
and
RCS
are active, LOW
and the FIFO is NOT empty.
SERIAL CLOCK (SCLK)
During serial loading of the programmng flag offset registers, a rising edge
on the SCLK input is used to load serial data present on the SI input provided
that the
SEN
input is LOW.
DATA OUTPUTS (Q
0
-Q
n
)
(Q
0
-Q
35
) are data outputs for 36-bit wide data, (Q
0
- Q
17
) are data outputs
for 18-bit wide data or (Q
0
-Q
8
) are data outputs for 9-bit wide data.
Figure 4. Echo Read Clock and Data Output Relationship
NOTES:
1.
REN
is LOW.
2. t
ERCLK
> t
A
, guaranteed by design.
3. Qslowest is the data output with the slowest access time, t
A
.
4. Time, t
D
is greater than zero, guaranteed by design.
5907 drw08
ERCLK
t
A
t
D
Q
SLOWEST
(3)
RCLK
t
ERCLK
t
ERCLK
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