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| 型號： | IDT72T36125L5BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 18/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 524X18 5NS 240BGA |
| 標準包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲容量： | 9.4K（524 x 18） |
| 數(shù)據(jù)速率： | 83MHz |
| 訪問時間： | 5ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應商設備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36125L5BBG |
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25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
marked location. During retransmit mode write operations to the device may
continue without hindrance.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode or
First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (
FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR)toindicatewhetherornotthere
is valid data at the data outputs (Qn). It also uses Input Ready (
IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK
rising edges,
REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (
REN) and RCLK.
AfterMasterReset,FWFT/SIactsasaserialinputforloading
PAEandPAF
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT
Standard and FWFT modes.
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedvia
ASYW,this
input behaves as WCLK.
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,the
FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating
HF flag to LOW). The Write and Read Clocks can either be
independent or coincident.
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe).
Data is Asynchronously written into the FIFO via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be tied LOW.
WRITE ENABLE (
WEN)
Whenthe
WENinput isLOW,datamaybeloadedintotheFIFORAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When
WENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode,
FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode,
IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle,
IR will go
LOW allowing a write to occur. The
IR flag is updated by two WCLK cycles +
tSKEW after the valid RCLK cycle.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
If Asynchronous operation of the write port has been selected, then WEN
must be held active, (tied LOW).
READ STROBE & READ CLOCK (RD/RCLK)
IfSynchronousoperationofthereadporthasbeenselectedvia
ASYR,this
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,the
EF/OR,PAE
and
HF flagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
the
HF flag to HIGH). The Write and Read Clocks can be independent or
coincident.
If Asynchronous operation has been selected this input is RD (Read
Strobe) . Data is Asynchronously read from the FIFO via the output register
whenever there is a rising edge on RD. In this mode the
REN and RCSinputs
mustbetiedLOW.The
OEinputisusedtoprovideAsynchronouscontrolofthe
three-stateQnoutputs.
WRITE CHIP SELECT (
WCS)
The
WCS disables all Write Port inputs (data only) if it is held HIGH. To
perform normal operations on the write port, the
WCS must be enabled, held
LOW.
READ ENABLE (
REN)
When Read Enable is LOW, data is loaded from the RAM array into the
outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.
When the
REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using
REN provided that
RCSisLOW. WhenthelastwordhasbeenreadfromtheFIFO,theEmptyFlag
(
EF)willgoLOW,inhibitingfurtherreadoperations. RENisignoredwhenthe
FIFO is empty. Once a write is performed,
EF will go HIGH allowing a read to
occur. The
EFflagisupdatedbytwoRCLKcycles+tSKEW afterthevalidWCLK
cycle. Both
RCS and REN must be active, LOW for data to be read out on the
rising edge of RCLK.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW
after the first write.
RENandRCSdonotneedtobeassertedLOW fortheFirst
Word to fall through to the output register. In order to access all other words,
a read must be executed using
REN and RCS. The RCLK LOW-to-HIGH
transition after the last word has been read from the FIFO, Output Ready (
OR)
will go HIGH with a true read (RCLK with
REN=LOW;RCS=LOW),inhibiting
further read operations.
REN is ignored when the FIFO is empty.
If Asynchronous operation of the Read port has been selected, then
REN
must be held active, (tied LOW).
SERIAL ENABLE (
SEN )
The
SENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset.
SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGH transition of SCLK.
When
SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded.
SEN functions the same way in both IDT
Standard and FWFT modes.
OUTPUT ENABLE (
OE)
When Output Enable is enabled (LOW), the parallel output buffers receive
datafromtheoutputregister. When
OEisHIGH,theoutputdatabus(Qn)goes
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| IDT72T36125L5BBGI | 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36125L5BBI | 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36125L6-7BB | 功能描述:IC FIFO 524X18 6-7NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML5BB | 功能描述:IC FIFO 1MX18 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML5BBG | 功能描述:IC FIFO 1MX18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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