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參數(shù)資料
| 型號： | IDT72T36115L10BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 19/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 131KX36 10NS 240BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲容量： | 4.7M（131K x 36） |
| 數(shù)據(jù)速率： | 50MHz |
| 訪問時間： | 10ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應(yīng)商設(shè)備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36115L10BB |
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26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
intoahighimpedancestate.DuringMasteroraPartialResetthe
OEistheonly
inputthatcanplacetheoutputbusQn,intoHigh-Impedance.DuringResetthe
RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
READ CHIP SELECT (
RCS )
The Read Chip Select input provides synchronous control of the Read
output port. When
RCS goes LOW, the next rising edge of RCLK causes the
QnoutputstogototheLow-Impedancestate. When
RCSgoesHIGH,thenext
RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master
orPartialResetthe
RCSinputhasnoeffectontheQnoutputbus,OEistheonly
inputthatprovidesHigh-ImpedancecontroloftheQnoutputs.If
OEisLOWthe
Qn data outputs will be Low-Impedance regardless of
RCSuntilthefirstrising
edge of RCLK after a Reset is complete. Then if
RCSisHIGHthedataoutputs
will go to High-Impedance.
The
RCSinputdoesnoteffecttheoperationoftheflags. Forexample,when
the first word is written to an empty FIFO, the
EFwillstillgofromLOWtoHIGH
based on a rising edge of RCLK
, regardless of the state of the RCS input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of
RCS. For this reason the user must take care when
adatawordiswrittentoanemptyFIFOinFWFTmode.If
RCSisdisabledwhen
anemptyFIFOiswritteninto,thefirstwordwillfallthroughtotheoutputregister,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take
RCSactiveLOWtoaccessthisfirstword,placetheoutputbusinLOW-Z.
RENmustremaindisabledHIGHforatleastonecycleafterRCShasgoneLOW.
A rising edge of RCLK with
RCS and REN active LOW, will read out the next
word. Care must be taken so as not to lose the first word written to an empty
FIFO when
RCSisHIGH.RefertoFigure17,RCS andREN ReadOperation
(FWFT Mode). The
RCS pin must also be active (LOW) in order to perform
aRetransmit. SeeFigure13forReadCycleandReadChipSelectTiming(IDT
Standard Mode). See Figure 16 for Read Cycle and Read Chip Select Timing
(First Word Fall Through Mode).
If Asynchronous operation of the Read port has been selected, then
RCS
must be held active, (tied LOW).
OE provides three-state control of Qn.
WRITE PORT HSTL SELECT (WHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththewriteport
can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master
Reset,thenHSTLoperationofthewriteportwillbeselected.IfWHSTLisLOW
at Master Reset, then LVTTL will be selected.
The inputs and outputs associated with the write port are listed in Table 5.
READ PORT HSTL SELECT (RHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththereadport
can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master
Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW
at Master Reset, then LVTTL will be selected for the read port, then echo clock
and echo read enable will not be provided.
The inputs and outputs associated with the read port are listed in Table 5.
SYSTEM HSTL SELECT (SHSTL)
Allinputsnotassociatedwiththewriteandreadportcanbesetuptobeeither
HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation
of all the inputs not associated with the write and read port will be selected. If
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs
associated with SHSTL are listed in Table 5.
LOAD (
LD)
This is a dual purpose pin. During Master Reset, the state of the
LDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
the
PAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
can be programmed, parallel or serial (see Table 2). After Master Reset,
LD
enables write operations to and read operations from the offset registers. Only
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offset registers can be read only in parallel.
AfterMasterReset,the
LDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvalues
PAEandPAF.PullingLDLOWwillbeginaserialloading
or parallel load or read of these offset values. THIS PIN MUST BE HIGH
AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO
MEMORY.
BUS-MATCHING (BM, IW, OW)
ThepinsBM,IWandOWareusedtodefinetheinputandoutputbuswidths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 5 for Bus-
Matching Byte Arrangement.
BIG-ENDIAN/LITTLE-ENDIAN (
BE )
During Master Reset, a LOW on
BE will select Big-Endian operation. A
HIGH on
BEduringMasterResetwillselectLittle-Endianformat.Thisfunction
is useful when the following input to output bus widths are implemented: x36 to
x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (
BE)pin.See
Figure 5 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Program-
mable flag timing mode. A HIGH on PFM will select Synchronous Program-
mable flag timing mode. If asynchronous
PAF/PAE configurationisselected
(PFM, LOW during
MRS), the PAE is asserted LOW on the LOW-to-HIGH
transition of RCLK.
PAE is reset to HIGH on the LOW-to-HIGH transition of
WCLK. Similarly, the
PAFisassertedLOWontheLOW-to-HIGHtransitionof
WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous
PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the
PAE isassertedandupdatedontherisingedgeofRCLKonlyand
notWCLK.Similarly,
PAFisassertedandupdatedontherisingedgeofWCLK
only and not RCLK. The mode desired is configured during master reset by
the state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity
mode. A HIGH will select Interspersed Parity mode. The IP bit function allows
the user to select the parity bit in the word loaded into the parallel port (D0-Dn)
whenprogrammingtheflagoffsets.IfInterspersedParitymodeisselected,then
the FIFO will assume that the parity bits are located in bit position D8, D17, D26
andD35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed
Parity mode is selected, then D8, D17 and D28 are is assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin.
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