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參數(shù)資料
| 型號(hào)： | IDT72T1875L6-7BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| 中文描述： | 2.5伏高速TeraSync先進(jìn)先出18-BIT/9-BIT配置 |
| 文件頁數(shù)： | 22/55頁 |
| 文件大小： | 540K |
| 代理商： | IDT72T1875L6-7BBI |
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22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
or both together. When
REN
and
LD
are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken fromthe fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permtted regardless of
which timng mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT FROMMARK OPERATION
The Retransmt fromMark feature allows FIFO data to be read repeatedly
starting at a user-selected position. The FIFO is first put into retransmt mode that
will mark’ a beginning word and also set a pointer that will prevent ongoing FIFO
write operations fromover-writing retransmt data. The retransmt data can be
read repeatedly any number of times fromthe marked position. The FIFO can
be taken out of retransmt mode at any time to allow normal device operation.
The mark’ position can be selected any number of times, each selection over-
writing the previous mark location. Retransmt operation is available in both IDT
standard and FWFT modes.
During IDT standard mode the FIFO is put into retransmt mode by a Low-
to-High transition on RCLK when the ‘MARK’ input is HIGH and
EF
is HIGH.
The rising RCLK edge marks’ the data present in the FIFO output register as
the first retransmt data. The FIFO remains in retransmt mode until a rising edge
on RCLK occurs while MARK is LOW.
Once a marked location has been set (and the device is still in retransmt
mode, MARK is HIGH), a retransmt can be initiated by a rising edge on RCLK
while the retransmt input (
RT
) is LOW.
REN
must be HIGH (reads disabled)
before bringing
RT
LOW. The device indicates the start of retransmt setup by
setting
EF
LOW, also preventing reads. When
EF
goes HIGH, retransmt setup
is complete and read operations may begin starting with the first data at the MARK
location. Since IDT standard mode is selected, every word read including the
first marked word following a retransmt setup requires a LOW on
REN
(read
enabled).
Note, write operations may continue as normal during all retransmt
functions, however write operations to the marked location will be prevented.
See Figure 18,
Retransmt fromMark (IDT standard mode)
, for the relevant
timng diagram
During FWFT mode the FIFO is put into retransmt mode by a rising RCLK
edge when the MARK’ input is HIGH and
OR
is LOW. The rising RCLK edge
‘marks’ the data present in the FIFO output register as the first retransmt data.
The FIFO remains in retransmt mode until a rising RCLK edge occurs while
MARK is LOW.
Once a marked location has been set (and the device is still in retransmt
can be initiated by a rising RCLK edge while the retransmt input (
RT
) is LOW.
REN
must be HIGH (reads disabled) before bringing
RT
LOW. The device
indicates the start of retransmt setup by setting
OR
HIGH.
When
OR
goes LOW, retransmt setup is complete and on the next rising
RCLK edge after retransmt setup is complete, (
RT
goes HIGH), the contents
of the first retransmt location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of
REN
, a
LOW on
REN
is not required for the first word. Reading all subsequent words
requires a LOW on
REN
to enable the rising RCLK edge. See Figure 19,
Retransmt fromMark timng (FWFT mode)
, for the relevant timng diagram
Note, for the IDT72T1845/72T1855/72T1865/72T1875/72T1885/
72T1895 there must be a mnimumof 32 bytes of data between the write pointer
and read pointer when the MARK is asserted, for the IDT72T18105/72T18115
there must be a mnimumof 128 bytes and for the IDT72T18125 there must be
a mnimumof 256 bytes. Remember, 2(x9) bytes = 1(x18) word. (32 bytes =
16 word = 8 long words). Also, once the MARK is set, the write pointer will not
increment past the “marked” location until the MARK is deasserted. This
prevents “overwriting” of retransmt data.
HSTL/LVTTL I/O
Both the write port and read port are user selectable between HSTL or
LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
control pins are selectable via SHSTL, see Table 5 for details of groupings.
Note, that when the write port is selected for HSTL mode, the user can reduce
the power consumption (in stand-by mode by utilizing the
WCS
input).
All “Static Pins” must be tied to VCC or GND. These pins are LVTTL only,
and are purely device configuration pins.
TABLE 5 — I/O CONFIGURATION
WHSTL SELECT
WHSTL: HIGH = HSTL
LOW = LVTTL
Dn (I/P)
WCLK/WR (I/P)
WEN
(I/P)
WCS
(I/P)
RHSTL SELECT
RHSTL: HIGH = HSTL
LOW = LVTTL
RCLK/RD (I/P)
RCS
(I/P)
MARK (I/P)
REN
(I/P)
OE
(I/P)
RT
(I/P)
Qn (O/P)
SHSTL SELECT
SHSTL: HIGH = HSTL
LOW = LVTTL
SCLK (I/P)
LD
(I/P)
MRS
(I/P)
TCK (I/P)
TMS (I/P)
SEN
(I/P)
FWFT/SI (I/P)
STATIC PINS
LVTTL ONLY
EF
/
OR
(O/P)
PAF
(O/P)
EREN
(O/P)
PAE
(O/P)
FF
/
IR
(O/P)
HF
(O/P)
ERCLK (O/P)
TDO (O/P)
PRS
(I/P)
TRST
(I/P)
TDI (I/P)
IW (I/P)
BM(I/P)
ASYR
(I/P)
IP (I/P)
FSEL1 (I/P)
SHSTL (I/P)
RHSTL (I/P)
OW (I/P)
ASYW
(I/P)
BE
(I/P)
FSEL0 (I/P)
PFM(I/P)
WHSTL (I/P)
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