IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
參數(shù)資料
型號: IDT72T1875L4-4BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 40/55頁
文件大?。?/td> 0K
描述: IC FIFO 16384X18 2.5V 4NS 144BGA
標準包裝: 1
系列: 72T
功能: 異步,雙端口
存儲容量: 288K(16K x 18)
數(shù)據(jù)速率: 10MHz
訪問時間: 3.4ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-BGA
供應(yīng)商設(shè)備封裝: 144-PBGA(13x13)
包裝: 托盤
其它名稱: 72T1875L4-4BB
45
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
NOTES:
1. m =
PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the IDT72T1885,
131,072 for the IDT72T1895, 262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576 for the IDT72T18125.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385 for the IDT72T1875,
32,769 for the IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105, 262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,
131,073 for the IDT72T1895, 262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577 for the IDT72T18125.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the
PAF deassertion time may be delayed one extra WCLK cycle.
4.
PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
6.
RCS is LOW.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAF
RCLK
REN
5909 drw27
1
2
12
D-(m+1) words
in FIFO
(2)
D - m words in FIFO
(2)
D - (m +1) words in FIFO
(2)
tENH
tENS
tPAFS
tENS
tENH
tCLKL
tSKEW2
(3)
tPAFS
tCLKL
NOTES:
1. n =
PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the
PAE deassertion may be delayed one extra RCLK cycle.
5.
PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7.
RCS = LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAE
RCLK
12
REN
5909 drw28
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
tENS
tSKEW2
(4)
tENH
tPAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
tPAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
tENS
tENH
tCLKH
tCLKL
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