參數(shù)資料
型號(hào): IDT72T18125L10BBI
廠商: Integrated Device Technology, Inc.
英文描述: 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
中文描述: 2.5伏高速TeraSync先進(jìn)先出18-BIT/9-BIT配置
文件頁(yè)數(shù): 53/55頁(yè)
文件大?。?/td> 540K
代理商: IDT72T18125L10BBI
53
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
WRITE CLOCK (WCLK)
m + n
m
n
MASTER RESET (
MRS
)
READ CLOCK (RCLK)
READ CHIP SELECT (
RCS
)
DATA OUT
n
m + n
WRITE ENABLE (
WEN
)
FULL FLAG/INPUT READY (
FF
/
IR
)
PROGRAMMABLE (
PAF
)
PROGRAMMABLE (
PAE
)
EMPTY FLAG/OUTPUT READY (
EF
/
OR
) #2
OUTPUT ENABLE (
OE
)
READ ENABLE (
REN
)
m
LOAD (
LD
)
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
FIFO
#1
EMPTY FLAG/OUTPUT READY (
EF
/
OR
) #1
PARTIAL RESET (
PRS
)
5909 drw40
FULL FLAG/INPUT READY (
FF
/
IR
) #2
HALF-FULL FLAG (
HF
)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (
RT
)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D
0
- D
m
DATA IN
D
m+1
- D
n
Q
0
- Qm
Q
m+1
- Q
n
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
SERIAL CLOCK (SCLK)
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected fromany one device.
The exceptions are the
EF
and
FF
functions in IDT Standard mode and the
IR
and
OR
functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for
EF
/
FF
deassertion and
IR
/
OR
assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing
EF
of every FIFO, and
separately ANDing
FF
of every FIFO. In FWFT mode, composite flags can be
created by ORing
OR
of every FIFO, and separately ORing
IR
of every FIFO.
Figure 36 demonstrates a width expansion using two IDT72T1845/
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125 devices. D
0
- D
17
fromeach device forma 36-bit wide input bus and
Q
0
-Q
17
fromeach device forma 36-bit wide output bus. Any word width can
be attained by adding additional IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125 devices.
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of Width Expansion
For the x18 Input or x18 Output bus Width: 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 18, 32,768 x 18, 65,536 x 36, 131,072 x 36,
262,144 x 36 and 524,288 x 36
For both x9 Input and x9 Output bus Widths: 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18,
524,288 x 18 and 1,048,576 x 18
相關(guān)PDF資料
PDF描述
IDT72T1845L5BB 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
IDT72T18115L5BB 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
IDT72T18125L5BB 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
IDT72T18115L10BB 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
IDT72T18115L10BBI 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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IDT72T18125L5BB 功能描述:IC FIFO 524X18 2.5V 5NS 240BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256(64 x 4) 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72T18125L5BBGI 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 524X18 2.5V 5NS 240BGA
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