參數(shù)資料
型號: IDT72T18105L6-7BBI
廠商: Integrated Device Technology, Inc.
英文描述: 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
中文描述: 2.5伏高速TeraSync先進先出18-BIT/9-BIT配置
文件頁數(shù): 27/55頁
文件大?。?/td> 540K
代理商: IDT72T18105L6-7BBI
27
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
If asynchronous
PAE
configuration is selected, the
PAE
is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK).
PAE
is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous
PAE
configuration is selected, the
PAE
is updated on the rising edge of RCLK. See
Figure 26,
Asynchronous Programmable Almost-Empty Flag Timng (IDT
Standard and FWFT Mode)
, for the relevant timng information.
HALF-FULL FLAG (
HF
)
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets
HF
LOW. The flag remains LOW until the difference
between the write and read pointers becomes less than or equal to half of the
total depth of the device; the rising RCLK edge that accomplishes this condition
sets
HF
HIGH.
In IDT Standard mode, if no reads are performed after reset (
MRS
or
PRS
),
HF
will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output
bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855,
8,192 for the IDT72T1865, 16,384 for the IDT72T1875, 32,768 for the
IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105,
262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, D = 4,096 for the IDT72T1845,
8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the
IDT72T1875, 65,536 for the IDT72T1885, 131,072 for the IDT72T1895,
262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576
for the IDT72T18125.
In FWFT mode, if no reads are performed after reset (
MRS
or
PRS
),
HF
will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus
Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855,
8,193 for the IDT72T1865, 16,385 for the IDT72T1875, 32,769 for the
IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105,
262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, D = 4,097 for the IDT72T1845,
8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the
IDT72T1875, 65,537 for the IDT72T1885, 131,073 for the IDT72T1895,
262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577
for the IDT72T18125.
See Figure 27,
Half-Full Flag Timng (IDT Standard and FWFT Mode)
,
for the relevant timng information. Because
HF
is updated by both RCLK and
WCLK, it is considered asynchronous.
ECHO READ CLOCK (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
selectable via RHSTL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of
REN
,
RCS
.
The ERCLK output follows the RCLK input with an associated delay. This
delay provides the user with a more effective read clock source when reading
data fromthe Qn outputs. This is especially helpful at high speeds when
variables within the device may cause changes in the data access times. These
variations in access time maybe caused by ambient temperature, supply
voltage, device characteristics. The ERCLK output also compensates for any
trace length delays between the Qn data outputs and receiving devices inputs.
Any variations effecting the data access time will also have a corresponding
effect on the ERCLK output produced by the FIFO device, therefore the ERCLK
output level transitions should always be at the same position in time relative to
the data outputs. Note, that ERCLK is guaranteed by design to be slower than
the slowest Qn, data output. Refer to Figure 4,
Echo Read Clock and Data
Output Relationship
, Figure 28,
Echo Read Clock & Read Enable Operation
and Figure 29,
Echo RCLK & Echo
REN
Operation
for timng information.
ECHO READ ENABLE (
EREN
)
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
selectable via RHSTL.
The
EREN
output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for reading
data fromthe Qn output port at high speeds. The
EREN
output is controlled by
internal logic that behaves as follows: The
EREN
output is active LOW for the
RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of
RCLK will cause
EREN
to go active, LOW if both
REN
and
RCS
are active, LOW
and the FIFO is NOT empty.
SERIAL CLOCK (SCLK)
During serial loading of the programmng flag offset registers, a rising edge
on the SCLK input is used to load serial data present on the SI input provided
that the
SEN
input is LOW.
DATA OUTPUTS (Q
0
-Q
n
)
(Q
0
- Q
17
) data outputs for 18-bit wide data or (Q
0
- Q
8
) data outputs for
9-bit wide data.
5909 drw08
ERCLK
t
A
t
D
Q
SLOWEST
(3)
RCLK
t
ERCLK
t
ERCLK
Figure 4. Echo Read Clock and Data Output Relationship
NOTES:
1.
REN
is LOW;
RCS
is LOW.
2. t
ERCLK
> t
A
, guaranteed by design.
3. Qslowest is the data output with the slowest access time, t
A
.
4. Time, t
D
is greater than zero, guaranteed by design.
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IDT72T18115L6-7BBI 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
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