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參數(shù)資料
| 型號： | IDT7290820PQF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 24/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 2048X2048 100-PQFP |
| 標準包裝： | 33 |
| 系列： | 7200 |
| 類型： | 多路復用器 |
| 電路： | 1 x 16:16 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應商設備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 7290820PQF |
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COMMERCIALTEMPERATURERANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
.UNCTIONAL DESCRIPTION
TheIDT7290820iscapableofswitchingupto2,048x2,048,64Kbit/sPCM
or N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channel basis.
The serial input streams of the IDT7290820 can have a bit rate of 2.048,
4.096 or 8.192 Mb/s and are arranged in 125
s wide frames, which contain
32,64or128channelsrespectively.Thedataratesoninputandoutputstreams
are identical.
In Processor Mode, the microprocessor can access input and output time-
slotsonaperchannelbasisallowingfortransferofcontrolandstatusinformation.
TheIDT7290820automaticallyidentifiesthepolarityoftheframesynchroniza-
tion input signal and configures the serial streams to either ST-BUS or GCI
formats.
With the variety of different microprocessor interfaces, IDT7290820 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfacesprovidecompatibilitywithmultiplexedandMotorolanon-multiplexed
buses. Thedevicecanalsoresolvedifferentcontrolsignalseliminatingtheuse
of glue logic necessary to convert the signals (R/
W/WR, DS/RD, AS/ALE).
Theframeoffsetcalibrationfunctionallowsuserstomeasuretheframeoffset
delay using a frame evaluation pin (FE). The input offset delay can be
programmedforindividualstreamsusinginternalframeinputoffsetregisters,see
Table 11.
The internal loopback allows the TX output data to be looped around to the
RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT7290820 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal serial-
to-parallel converters and stored sequentially in the data memory. The 8KHz
input frame pulse (
F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 2,048 bytes.
Data to be output on the serial streams (TX0-15) may come from either the
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
tobeoutputfromconnectionmemory,theconnectionmemorycontrolbitsmust
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
IntheConnectionMode,theaddressesoftheinputsourcedataforalloutput
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
theoutputstreams.Fordetailsontheuseofthesourceaddressdata(CABand
SAB bits), see Table 13 and Table 14. Once the source address bits are
programmed by the microprocessor, the contents of the data memory at the
selected address are transferred to the parallel-to-serial converters and then
onto a TX output stream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a particular
outputstreamandchannelnumberandistransferreddirectlytotheparallel-to-
serial converter one time-slot before it is to be output. This data will be output
ontheTXstreamsineveryframeuntilthedataischangedbythemicroprocessor.
AstheIDT7290820canbeusedinawidevarietyofapplications,thedevice
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT7290820 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function.Inaddition,oneofthesebitsallowstheusertocontroltheCCOoutput.
Ifanoutputchannelissettoahigh-impedancestatethroughtheconnection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS
outputscanbeplacedinahighimpedancestatebyeitherpullingtheODEinput
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connectionmemorybits.
The connection memory data can be accessed via the microprocessor
interface.Theaddressingofthedevicesinternalregisters,dataandconnection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 4, 6 and 7).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
data rates of 2.048, 4.096 or 8.192 Mb/s, the master clock (CLK) must be either
at 4.096, 8.192 or 16.384 MHz respectively. The input and output stream data
rates will always be identical.
The IDT7290820 provides two different interface timing modes ST-BUS/
GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT7290820
is in the wide frame pulse (WFP) frame alignment mode.
In ST-BUS/GCI mode, the input 8 KHz frame pulse can be in either
ST-BUS or GCI format. The IDT7290820 automatically detects the presence
of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS
format, every second falling edge of the master clock marks a bit boundary and
the data is clocked in on the rising edge of CLK, three quarters of the way into
the bit cell, see Figure 7. In GCI format, every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell, see Figure 8.
WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING
When the device is in WFP frame alignment mode, the CLK input must be
at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 KHz frame pulse
isinST-BUSformat.ThetimingrelationshipbetweenCLK,HCLKandtheframe
pulse is shown in Figure 9.
WhenWFPSpinishigh,theframealignmentevaluationfeatureisdisabled.
However,theframeinputoffsetregistersmaystillbeprogrammedtocompensate
for the varying frame delays on the serial input streams.
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