參數資料
型號： IDT7290820BC
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 路由/交換
英文描述： TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA100
封裝： 11 X 11 MM, 1 MM PITCH, BGA-100
文件頁數： 7/27頁
文件大?。?/td> 174K
代理商： IDT7290820BC
7
COMMERCIAL TEMPERATURE RANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
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The IDT7290820 can operate at different speeds. To configure the
maximumnon-blocking switching data rate, the two DR bits in the IMS register
are used. Following are the possible configurations:
2.048 Mb/s Serial Links (DR0=0, DR1=0)
When the 2.048 Mb/s data rate is selected, the device is configured with
16-input/16-output data streams each having 32, 64 Kbit/s channels each. This
mode requires a CLK of 4.096 MHz and allows a maximumnon-blocking
capacity of 512 x 512 channels.
4.096 Mb/s Serial Links (DR0=1, DR1=0)
When the 4.096 Mb/s data rate is selected, the device is configured with
16-input/16-output data streams each having 64, 64 Kbit/s channels each. This
mode requires a CLK of 8.192 MHz and allows a maximumnon-blocking
capacity of 1,024 x 1,024 channels.
8.192 Mb/s Serial Links (DR0=0, DR1=1)
When the 8.192 Mb/s data rate is selected, the device is configured with
16-input/16-output data streams each having 128, 64 Kbit/s channels each. This
mode requires a CLK of 16.384 MHz and allows a maximumnon-blocking
capacity of 2,048 x 2,048 channels.
Table 1 summarizes the switching configurations and the relationship
between different serial data rates and the master clock frequencies.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output streamchannel alignment (i.e.
F0i
).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
data is often delayed, this feature is useful in compensating for the skew between
clocks.
Each input streamcan have its own delay offset value by programmng the
frame input offset registers (FOR). The maximumallowable skew is +4.5 master
clock (CLK) periods forward with resolution of 1/2 clock period. The output frame
offset cannot be offset or adjusted. See Figure 5, Table 11 and 12 for delay offset
programmng.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT7290820 provides the frame evaluation (FE) input to determne
different data input delays with respect to the frame pulse
F0i
.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the IMS register is changed
fromlow to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes fromlow
to high to signal that a valid offset measurement is ready to be read frombits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle started.
In ST-BUS
mode, the falling edge of the frame measurement signal (FE)
is evaluated against the falling edge of the ST-BUS
frame pulse. In GCI mode,
the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 10 & Figure 4 for the description of the frame alignment register.
This feature is not available when the WFP Frame Alignment mode is
enabled (i.e., when the WFPS pin is connected to VCC).
MEMORY BLOCK PROGRAMMING
The IDT7290820 provides users with the capability of initializing the entire
connection memory block in two frames. To set bits 11 to 15 of every connection
memory location, first programthe desired pattern in bits 5 to 9 of the IMS register.
The block programmng mode is enabled by setting the memory block
program(MBP) bit of the control register high. When the block programmng
enable (BPE) bit of the IMS register is set to high, the block programmng data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programmng is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
The loopback control (LPBK) bit of each connection memory location allows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data fromTX n channel mroutes to
the RX n channel minternally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
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The switching of information fromthe input serial streams to the output serial
streams results in a throughput delay. The device can be programmed to
performtime-slot interchange functions with different throughput delay capabili-
ties on the per-channel basis. For voice applications, variable throughput delay
is best as it ensures mnimumdelay between input and output data. In wideband
data applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the
V
/C bit of the connection memory.
VARIABLE DELAY MODE (
V
/C BIT = 0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
mnimumdelay achievable in the IDT7290820 is three time-slots. If the input
channel data is switched to the same output channel (channel n, frame p), it will
be output in the following frame (channel n, frame p+1). The same is true if input
channel n is switched to output channel n+1 or n+2. If the input channel n is
switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 2 shows the possible delays for the IDT7290820 in the
variable delay mode.
Serial Interface
Data Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Master Clock Required
(MHz)
4.096
8.192
16.384
Matrix
Channel
Capacity
512 x 512
1,024 x 1,024
2,048 x 2,048
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參數描述
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