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參數資料
| 型號： | IDT728985 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | TIME SLOT INTERCHANGE DIGITAL SWITCH |
| 中文描述： | 時隙交換數字開關 |
| 文件頁數： | 3/13頁 |
| 文件大?。?/td> | 117K |
| 代理商： | IDT728985 |
3
Commercial Temperature Range
IDT728985 Time Slot Interchange
Digital Switch 256 x 256
eight output (TX0-7) serial streams are provided in the IDT728985 device
allowing a complete 256 x 256 channel non-blocking switch matrix to be
constructed. The serial interface clock for the device is 4.096 MHz, as required
in ST-BUS
and GCI specifications.
The received serial data is internally converted to parallel by the on chip
serial-to-parallel converters and stored sequentially in a 256-position Data
Memory. By using an internal counter that is reset by the input 8 KHz frame pulse,
F0i,
the incomng serial data streams can be framed and sequentially addressed.
Depending on the type of information to be switched, the IDT728985 device
can be programmed to performtime slot interchange functions with different
throughput delay capabilities on a per-channel basis. The Variable Delay
mode, most commonly used for voice applications, can be selected ensuring
mnimumthroughput delay between input and output data. In Constant Delay
mode, used in multiple or grouped channel data applications, the integrity of the
information through the switch is maintained.
CONNECTION MEMORY
Data to be output on the serial streams may come fromtwo sources: Data
Memory or Connection Memory. The Connection Memory is split into HIGH
and LOW parts and is associated with particular TX output streams. In Processor
Mode, data output on the TX streams is taken fromthe Connection Memory Low
and originates fromthe mcroprocessor (Figure 2). Where as in Connection
Mode (Figure 1), data is read fromData Memory and originated fromthe
incomng RX streams. Data destined for a particular channel on the serial output
streamis read internally during the previous channel time slot to allow time for
memory access and internal parallel-to-serial conversion.
CONNECTION MODE
In Connection Mode, the addresses of input source for all output channels
are stored in the Connection Memory Low. The Connection Memory Low
locations are mapped to corresponding 8-bit x 32-channel outputs. The contents
of the Data Memory at the selected address are then transferred to the parallel-
to-serial converters before being output. By having the output channel to specify
the input channel through the Connection Memory, the same input channel can
be broadcast to several output channels.
PROCESSOR MODE
In Processor Mode the CPU writes data to the Connection Memory Low
locations which correspond to the output link and channel number. The contents
of the Connection Memory Low are transferred to the parallel-to-serial
converter one channel before it is to be output and are transmtted each frame
to the output until it is changed by the CPU.
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
functions available in the IDT728985. Output channels are selected into specific
modes such as: Processor Mode or Connection mode, Variable or Constant
throughput delay modes, Output Drivers Enabled or in three-state condition.
There is also one bit to control the state of the CCO output pin.
OUTPUT DRIVE ENABLE (ODE)
The ODE pin is the master output three-state control pin. If the ODE input
is held LOW all TDM(Time Division Multiplexed) outputs will be placed in high
impedance regardless Connection Memory High programmng. However, if
ODE is HIGH, the contents of Connection Memory High control the output state
on a per-channel basis.
SERIAL INTERFACE TIMING
The IDT728985 master clock (
C4i
) is 4.096 MHz signal allowing serial data
link configuration at 2.048 Mb/s to be implemented. The IDT728985 can
automatically detect the presence of an input frame pulse, identify the type of
backplane present on the serial interface, and format the synchronization pulse
according to ST-BUS
or GCI interface specifications (active HIGH in GCI or
active LOW in ST-BUS
). Upon determning the correct interface Connected
to the serial port, the internal timng unit establishes the appropriate serial data
bit transmt and sampling edges. In ST-BUS
mode, every second falling edge
of the 4.096 MHz clock marks a boundary and the input data is clocked in by
the rising edge, three quarters of the way into the bit cell. In GCI mode every
second rising edge of the 4.096 MHz clock marks the bit boundary while data
sampling is performed during the falling edge, at three quarters of the bit
boundaries.
The transfer of information fromthe input serial streams to the output serial
streams results in a delay through the device. The delay through the IDT728985
device varies according to the mode selected in the
V
/C bit of the Connection
Memory High.
VARIABLE DELAY MODE
The delay in Variable Delay Mode is dependent only on the combination
of source and destination on the input and output streams. The mnimumdelay
achievable in the IDT728985 device is three time slots. In the IDT728985
device, the information that is to be output in the same channel position as the
information is input (position n), relative to frame pulse, will be output in the
following frame (channel n, frame n+1). The same occurs if the input channels
succeeding (n+1, n+2) the channel position as the information is input.
The information switched to the third time slot after the input has entered the
device (for instance, input channel 0 to output channel 3 or input channel 30 to
output channel 1), is always output three channels later.
Any switching configuration that provides three or more time slots between
input and output channels, will have a throughput delay equal to the difference
Figure 2. Processor Mode
Figure 1. Connection Mode
Receive
Serial Data
Streams
5708 drw05
RX
TX
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
5708 drw06
TX
Microprocessor
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
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| IDT728985J | 功能描述:IC DGTL SW 256X256 44-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關，多路復用器，解碼器 系列:7200 標準包裝:48 系列:74VHC 類型:多路復用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:管件 |
| IDT728985J8 | 功能描述:IC DGTL SW 256X256 44-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關，多路復用器，解碼器 系列:7200 標準包裝:48 系列:74VHC 類型:多路復用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:管件 |
| IDT728985JG | 功能描述:IC DGTL SW 256X256 44-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - 信號開關，多路復用器，解碼器 系列:7200 標準包裝:1 系列:74LVC 類型:解碼器/多路分解器 電路:1 x 2:4 獨立電路:2 輸出電流高，低:24mA，24mA 電壓電源:單電源 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.209"，5.30mm 寬） 供應商設備封裝:16-SO 包裝:Digi-Reel® 其它名稱:296-28947-6 |
| IDT728985JG8 | 功能描述:IC DGTL SW 256X256 44-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - 信號開關，多路復用器，解碼器 系列:7200 標準包裝:48 系列:74VHC 類型:多路復用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:管件 |
| IDT7290820J | 功能描述:IC DGTL SW 2048X2048 84-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關，多路復用器，解碼器 系列:7200 標準包裝:48 系列:74VHC 類型:多路復用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:管件 |
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