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參數(shù)資料
| 型號(hào)： | IDT728981J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 路由/交換 |
| 英文描述： | TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128 |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQCC44 |
| 封裝： | 0.650 X 0.650 INCH, 1.27 MM PITCH, PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 91K |
| 代理商： | IDT728981J |
4
C
ommercial Temperature Range
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
!
If the A5 address line input is LOW then the IDT728981 Internal Control
Register is addressed. If A5 input line is high, then the remaining address input
lines are used to select the 32 possible channels per input or output stream The
address input lines and the StreamAddress bits (STA) of the Control register
give the user the capability of selecting all positions of IDT728981 Data and
Connection memories. The IDT728981 memory mapping is illustrated in Table
2 and Figure 3.
The data in the control register (Table 3) consists of Memory Select and
StreamAddress bits, Split Memory and Processor Mode bits. In Split Memory
mode (Bit 7 of the Control register) reads are fromthe Data Memory and writes
are to the Connection Memory as specified by the Memory Select Bits (Bits 4
and 3 of the Control Register). The Memory Select bits allow the Connection
Memory HIGH or LOW or the Data Memory to be chosen, and the Stream
Address bits define internal memory subsections corresponding to input or
output streams.
The Processor Enable bit (bit 6) places EVERY output channel on every
output streamin Processor mode; i.e., the contents of the Connection Memory
LOW (CML, see Table 5)) are output on the TX output streams once every frame
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT728981 behaves
as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection
Memory High (CMH) locations were set to HIGH, regardless of the actual value.
Connection Memory High
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 1
Channel 1
Channel 1
Channel 2
Channel 2
Channel 2
Channel 2
Channel 31
Channel 31
Channel 31
Channel 31
100001
100010
111111
Data Memory
0
0
0
0
1
1
1
0
1
1
2
3
0
1
1
1
0
1
100000
Connection Memory Low
Stream
Control Register
CR
b
7
External Address Bits A5-A0
5703 drw07
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
CR
b
6
CR
b
5
CR
b
4
CR
b
3
CR
b
2
CR
b
1
CR
b
0
CR
b
1
CR
b
0
CR
b
4
CR
b
3
Figure 3. Address Mapping
If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
the CML define the source information (streamand channel) of the time slot that
is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) the output streamand channel.
INITIALIZATION OF THE IDT728981
On initialization or power up, the contents of the Connection Memory High
can be in any state. This is a potentially hazardous condition when multiple TX
outputs are tied together to formmatrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
During the mcroprocessor initialization routine, the mcroprocessor should
programthe desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two connected TX
outputs drive the bus simultaneously. With the CMH setup, the mcroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
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| IDT728981JG | 功能描述:IC DGTL SWITCH ST-BUS 44-PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 邏輯 - 信號(hào)開(kāi)關(guān)，多路復(fù)用器，解碼器 系列:- 標(biāo)準(zhǔn)包裝:48 系列:74VHC 類(lèi)型:多路復(fù)用器 電路:4 x 2:1 獨(dú)立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| IDT728981JG8 | 功能描述:IC DGTL SW 256X256 44-PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 邏輯 - 信號(hào)開(kāi)關(guān)，多路復(fù)用器，解碼器 系列:7200 標(biāo)準(zhǔn)包裝:48 系列:74VHC 類(lèi)型:多路復(fù)用器 電路:4 x 2:1 獨(dú)立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
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