參數(shù)資料
型號(hào)： IDT72851L25TFI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： DUAL CMOS SyncFIFO
中文描述： 8K X 9 BI-DIRECTIONAL FIFO, 15 ns, PQFP64
封裝： SLIM, TQFP-64
文件頁(yè)數(shù)： 15/16頁(yè)
文件大?。?/td> 169K
代理商： IDT72851L25TFI
15
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
data according to type, sending one kind to FIFO A and the other kind to FIFO
B. Then, at the outputs, each data type is transferred to its appropriate
destination. Additional IDT72801/72811/72821/72831/72841/72851s permt
more than two priority levels. Priority buffering is particularly useful in network
applications.
The two FIFOs contained in the IDT72801/72811/72821/72831/72841/
72851 can be used to prioritize two different types of data shared on a system
bus. When writing fromthe bus to the FIFO, control logic sorts the intermxed
Figure 16. Block Diagram of Two Priority Configuration
The two FIFOs of the IDT72801/72811/72821/72831/72841/72851 can
be used to buffer data flow in two directions. In the example that follows, a
processor can write data to a peripheral controller via FIFO A, and, in turn,
the peripheral controller can write the processor via FIFO B.
Figure 17. Block Diagram of Bidirectional Configuration
RAM ARRAY A
Processor
Data
D
A0
-D
A8
Q
A0
-Q
A8
WENA2
OEA
RENA
Address
Control
IDT
72801
72811
72821
72831
72841
72851
D
B0
-D
B8
Q
B0
-Q
B8
WENB2
OEB2
RENB1
WENB1
C
L
RAM
9
RCLKA
WCLKB
9
9
9
9
WCLKA
WENA1
RAM ARRAY B
Clock
RCLKB
RENB2
RENA2
V
CC
V
CC
9
9
Voice Processing
Card
Data
I/O Data
Clock
C
L
Address
Control
Image Processing
Card
Clock
Data
I/O Data
C
L
Address
Control
3034 drw 17
RAM ARRAY A
WENA2
RENA2
Processor
Peripheral
Controller
DMA Clock
Data
DA0-DA8
QA0-QA8
IDT
72801
72811
72821
72831
72841
72851
RAM ARRAY B
Data
OEA
RENA1
Address
Control
I/O Data
DB0-DB8
WENB2
QB0-QB8
OEB
WENB1
RAM
9
9
RCLKA
WCLKB
9
9
9
9
9
9
WCLKA
WENA1
RENB1
Clock
RCLKB
C
L
Address
Control
9
RENB2
V
CC
3034 drw 18
C
L
相關(guān)PDF資料
PDF描述
IDT728980 TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256
IDT728981 TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
IDT728981DB TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
IDT728981J TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
IDT728981P TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72851L25TFI8 功能描述:IC FIFO SYNC DUAL 8192X9 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT7285L12PA 功能描述:IC FIFO 4096X18 12NS 56TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT7285L12PA8 功能描述:IC FIFO 4096X18 12NS 56TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT7285L12PAG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 4096X18 12NS 56TSSOP
IDT7285L12PAG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 4096X18 12NS 56TSSOP
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