參數(shù)資料
型號(hào)： IDT72845LB15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
中文描述： 4K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 11/26頁(yè)
文件大小： 334K
代理商： IDT72845LB15PF
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
When the
LD
pin is LOW and
WEN
is HIGH, the WCLK input is disabled;
then a signal at this input can neither increment the write offset register
pointer, nor execute a write.
The contents of the offset registers can be read on the output lines when
the
LD
pin is set LOW and
REN
is set LOW; then, data can be read on the
LOW-to-HIGH transition of the Read clock (RCLK). The act of reading the
control registers employs a dedicated read offset register pointer. (The read
and write pointers operate independently). Offset register content can be
read out in the IDT Standard mode only. It is inhibited in the FWFT mode.
A read and a write should not be performed simultaneously to the offset
registers.
FIRST LOAD (
FLA
/
FLB
)
For the single device mode, see Table I for additional information. In the
Daisy Chain Depth Expansion configuration,
FLA
/
FLB
is grounded to
indicate it is the first device loaded and is set to HIGH for all other devices
in the Daisy Chain. (See Operating Configurations for further details.)
WRITE EXPANSION INPUT (
WXIA
/
WXIB
)
This is a dual purpose pin. For single device mode, see Table I for
additional information.
WXIA
/
WXIB
is connected to Write Expansion Out
(
WXOA
/
WXOB
) of the previous device in the Daisy Chain Depth Expansion
mode.
READ EXPANSION INPUT (
RXIA
/
RXIB
)
This is a dual purpose pin. For single device mode, see Table I for
additional information.
RXIA
/
RXIB
is connected to Read Expansion Out
(
RXOA
/
RXOB
) of the previous device in the Daisy Chain Depth Expansion
mode.
OUTPUTS:
FULL FLAG/INPUT READY (
FFA
/
IRA
,
FFB
/
IRB
)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FFA
/
FFB
) function is selected. When the FIFO is full,
FF
will go LOW, inhibiting
further write operations. When
FF
is HIGH, the FIFO is not full. If no reads
are performed after a reset,
FF
will go LOW after D writes to the FIFO. D =
256 writes for the IDT72805LB, 512 for the IDT72815LB, 1,024 for the
IDT72825LB, 2,048 for the IDT72835LB and 4,096 for the IDT72845LB.
In FWFT mode, the Input Ready (
IRA
/
IRB
) function is selected.
IR
goes
LOW when memory space is available for writing in data. When there is no
longer any free space left,
IR
goes HIGH, inhibiting further write operations.
IR
will go HIGH after D writes to the FIFO. D = 257 writes for the
IDT72805, 513 for the IDT72815, 1,025 for the IDT72825, 2,049 for the
IDT72835 and 4,097 for the IDT72845. Note that the additional word in
FWFT mode is due to the capacity of the memory plus output register.
FF
/
IR
is synchronous and updated on the rising edge of WCLK.
EMPTY FLAG/OUTPUT READY (
EFA
/
ORA
,
EFB
/
ORB
)
This is a dual purpose pin. In the IDT Standard mode, the
Empty Flag
(
EFA
/
EFB
) function is selected. When the FIFO is
empty,
EF
will go LOW,
inhibiting further read operations. When
EF
is HIGH, the FIFO is not empty.
In FWFT mode, the Output Ready (
ORA
/
ORB
) function is selected.
OR
goes LOW at the same time that the first word written to an empty FIFO
appears valid on the outputs.
OR
stays LOW after the RCLK LOW to HIGH
transition that shifts the last word fromthe FIFO memory to the outputs.
OR
goes HIGH only with a true read (RCLK with
REN
= LOW). The previous
data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until
OR
goes LOW again.
EF
/
OR
is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (
PAFA
/
PAFB
)
The Programmable Almost-Full flag (
PAFA
/
PAFB
) will go LOW when
FIFO reaches the almost-full condition. In IDT Standard mode, if no reads
are performed after Reset (
RS
), the
PAF
will go LOW after (256-m writes for
the IDT72805LB, (512-m writes for the IDT72815LB, (1,024-m writes for
the IDT72825LB, (2,048–m writes for the IDT72835LB and (4,096–m writes
for the IDT72845LB. The offset “m” is defined in the Full Offset register.
In FWFT mode, if no reads are performed,
PAF
will go LOW after (257-
m writes for the IDT72805LB, (513-m writes for the IDT72815LB, (1,025-
m writes for the IDT72825LB, (2,049-m writes for the IDT72835LB and
(4,097-m writes for the IDT72845LB. The default values for mare noted in
Table 1 and 2.
If asynchronous
PAF
configuration is selected, the
PAF
is asserted
LOW on the LOW-to-HIGH transition of the Write Clock (WCLK).
PAF
is
reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If
synchronous
PAF
configuration is selected (see Table I), the
PAF
is
updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAEA
/
PAEB
)
The
PAE
flag will go LOW when the FIFO reads the almost-empty
condition. In IDT Standard mode,
PAE
will go LOW when there are n words
or less in the FIFO. In FWFT mode, the
PAE
will go LOW when there are
n+1 words or less in the FIFO. The offset “n” is defined as the Empty offset.
The default values for n are noted in Table 1 and 2.
If asynchronous
PAE
configuration is selected, the
PAE
is asserted
LOW on the LOW-to-HIGH transition of the Read Clock (RCLK).
PAE
is
reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK).
If synchronous
PAE
configuration is selected (see Table I), the
PAE
is
updated on the rising edge of RCLK.
WRITE EXPANSION OUT/HALF-FULL FLAG
(
WXOA
/
HFA
,
WXOB
/
HFB
)
This is a dual-purpose output. In the Single Device and Width Expansion
mode, when Write Expansion In (
WXIA
/
WXIB
) and/or Read Expansion In
(
RXIA
/
RXIB
) are grounded, this output acts as an indication of a half-full
memory.
After half of the memory is filled, and at the LOW-to-HIGH transition of
the next write cycle, the Half-Full flag goes LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full flag (
HFA
/
HFB
)
is then reset to HIGH by the LOW-to-HIGH transition of the Read Clock
(RCLK). The
HF
is asynchronous.
In the Daisy Chain Depth Expansion mode,
WXI
is connected to
WXO
of the previous device. This output acts as a signal to the next device in the
Daisy Chain by providing a pulse when the previous device writes to the last
location of memory.
READ EXPANSION OUT (
RXOA
/
RXOB
)
In the Daisy Chain Depth Expansion configuration, Read Expansion In
(
RXIA
/
RXIB
) is connected to Read Expansion Out (
RXOA
/
RXOB
) of the
previous device. This output acts as a signal to the next device in the Daisy
Chain by providing a pulse when the previous device reads fromthe last
location of memory.
DATA OUTPUTS (Q
0
-Q
17
, QB
0
-QB
17
)
Q0-Q17 are data outputs for 18-bit wide data.
相關(guān)PDF資料
PDF描述
IDT72825LB20BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
IDT72805LB25BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
IDT72815LB25BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
IDT72825LB25BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
IDT72805LB10BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72845LB15PF8 功能描述:IC FIFO SYNC DL 4096X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72845LB15PFI 功能描述:IC FIFO SYNC DL 4096X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72845LB15PFI8 功能描述:IC FIFO SYNC DL 4096X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72845LB25PF 功能描述:IC FIFO SYNC DL 4096X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72845LB25PF8 功能描述:IC FIFO SYNC DL 4096X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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