參數(shù)資料
型號： IDT72841L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： DUAL CMOS SyncFIFO
中文描述： 4K X 9 BI-DIRECTIONAL FIFO, 10 ns, PQFP64
封裝： TQFP-64
文件頁數(shù)： 6/21頁
文件大?。?/td> 228K
代理商： IDT72841L15PF
5.15
6
COMMERCIAL TEMPERATURE
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
Read Clock (RCLKA, RCLKB)
— Data can be read from
Array A (B) on the the LOW-to-HIGH transition of RCLKA
(RCLKB). The Empty Flag
EFA
(
EFB
) and Programmable
Almost-Empty Flag
PAEA
(
PAEB
) are synchronized with re-
spect to the LOW-to-HIGH transition of RCLKA (RCLKB).
The write and read clock can be asynchronous or coinci-
dent.
Read Enables (
both Read Enables
RENA1
,
RENA2
(
RENB1
,
RENB2
) are
LOW, data is read from Array A (B) to the output register on the
LOW-to-HIGH transition of the read clock RCLKA (RCLKB).
When either of the two Read Enable
RENA1
,
RENA2
(
RENB1
,
RENB2
) associated with FIFO A (B) is HIGH, the
output register holds the previous data and no new data is
allowed to be loaded into the register.
When all the data has been read from FIFO A (B), the
Empty Flag
EFA
(
EFB
) will go LOW, inhibiting further read
operations. Once a valid write operation has been accom-
plished,
EFA
(
EFB
) will go HIGH after t
REF
and a valid read can
begin. The Read Enables
RENA1
,
RENA2
(
RENB1
,
RENB2
)
are ignored when FIFO A (B) is empty.
RENA1
,
RENA2
,
RENB1
,
RENB2
)
— When
Output Enable (
OEA
(
OEB
) is enabled (LOW), the parallel output buffers of FIFO A
(B) receive data from their respective output register. When
Output Enable
OEA
(
OEB
) is disabled (HIGH), the QA (QB)
output data bus is in a high-impedance state.
,
OEB
)
— When Output Enable
OEA
Write Enable 2/Load (WENA2/
is a dual-purpose pin. FIFO A (B) is configured at Reset to
have programmable flags or to have two write enables, which
allows depth expansion. If WENA2/
LDA
(WENB2/
LDB
)
is set
HIGH at Reset
RSA
= LOW (
RSB
= LOW), this pin operates as
a second write enable pin.
If FIFO A (B) is configured to have two write enables, when
Write Enable 1
WENA1
(
WENB1
) is LOW and WENA2/
LDA
(WENB2/
LDB
) is HIGH, data can be loaded into the input
register and RAM array on the LOW-to-HIGH transition of
every write clock WCLKA (WCLKB). Data is stored in the
array sequentially and independently of any on-going read
operation.
In this configuration, when
WENA1
(
WENB1
) is HIGH and/
or WENA2/
LDA
(WENB2/
LDB
) is LOW, the input register of
Array A holds the previous data and no new data is allowed to
be loaded into the register.
To prevent data overflow, the Full Flag
FFA
(
FFB
) will go
LOW, inhibiting further write operations. Upon the completion
of a valid read cycle,
FFA
(
FFB
) will go HIGH after t
WFF
, al-
lowing a valid write to begin.
WENA1
, (
WENB1
) and WENA2/
LDA
(WENB2/
LDB
) are ignored when the FIFO is full.
FIFO A (B) is configured to have programmable flags when
the WENA2/
LDA
(WENB2/
LDB
) is set LOW at Reset
RSA
=
LOW (
RSB
= LOW). Each FIFO contains four 8-bit offset
registers which can be loaded with data on the inputs, or read
on the outputs. See Figure 3 for details of the size of the
registers and the default values.
LDA
, WENB2/
LDB
)
— This
SIGNAL DESCRIPTIONS
FIFO A and FIFO B are identical in every respect. The
following description explains the interaction of input and
output signals for FIFO A. The corresponding signal names
for FIFO B are provided in parentheses.
INPUTS:
Data In (D
A0
– D
A8
, D
B0
– D
B8
) —
D
A0
- D
A8
are the nine
data inputs for memory array A. D
B0
- D
B8
are the nine data
inputs for memory array B.
CONTROLS:
Reset (
RSA
whenever
RSA
(
RSB
) input is taken to a LOW state. During
reset, the internal read and write pointers associated with the
FIFO are set to the first location. A reset is required after
power-up before a write operation can take place. The Full
Flag
FFA
(
FFB
) and Programmable Almost-Full Flag
PAFA
(
PAFB
) will be reset to HIGH after t
RSF
. The Empty Flag
EFA
(
EFB
) and Programmable Almost-Empty Flag
PAEA
(
PAEB
) will
be reset to LOW after t
RSF
. During reset, the output register
is initialized to all zeros and the offset registers are initialized
to their default values.
,
RSB
)
—
Reset of FIFO A (B) is accomplished
Write Clock (WCLKA, WCLKB)
—
A write cycle to Array
A (B) is initiated on the LOW-to-HIGH transition of WCLKA
(WCLKB). Data set-up and hold times must be met with
respect to the LOW-to-HIGH transition of WCLKA (WCLKB).
The Full Flag
FFA
(
FFB
) and Programmable Almost-Full Flag
PAFA
(
PAFB
) are synchronized with respect to the LOW-to-
HIGH transition of the write clock WCLKA (WCLKB).
The write and read clocks can be asynchronous or coinci-
dent.
Write Enable 1 (
WENA1
figured for programmable flags,
WENA1
(
WENB1
) is the only
enable control pin. In this configuration, when
WENA1
(
WENB1
)
is LOW, data can be loaded into the input register of RAM
Array A (B) on the LOW-to-HIGH transition of every write clock
WCLKA (WCLKB). Data is stored in Array A (B) sequentially
and independently of any on-going read operation.
In this configuration, when
WENA1
(
WENB1
) is HIGH, the
input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which
allows for depth expansion. See Write Enable 2 paragraph
below for operation in this configuration.
To prevent data overflow,
FFA
(
FFB
) will go LOW, inhibiting
further write operations. Upon the completion of a valid read
cycle, the
FFA
(
FFB
) will go HIGH after t
WFF
, allowing a valid
write to begin.
WENA1
(
WENB1
) is ignored when FIFO A (B)
is full.
,
WENB1
)
— If FIFO A (B) is con-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72841L-15PF 制造商:Integrated Device Technology Inc 功能描述:FIFO, 2 x 4K x 9, Synchronous, 64 Pin, Plastic, QFP
IDT72841L15PF8 功能描述:IC FIFO SYNC 4KX9 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72841L15PFG 功能描述:IC FIFO SYNC 4KX9 15NS 64QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984
IDT72841L15PFI 功能描述:IC FIFO SYNC 4KX9 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72841L15PFI8 功能描述:IC FIFO SYNC 4KX9 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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