IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOT" />
參數(shù)資料
型號: IDT72835LB25PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 11/26頁
文件大?。?/td> 0K
描述: IC FIFO SYNC DL 2048X18 128TQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲容量: 36.8K(2K x 18)
數(shù)據(jù)速率: 40MHz
訪問時(shí)間: 25ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 72835LB25PF8
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
JANUARY 13, 2009
Figure
21.
Read
Timing
with
Synchronous
Programmable
Flags
(FWFT
Mode)
NOTES:
1.
tSKEW1
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
IR
will
go
LOW
after
one
WCLK
plus
t
WFF
.If
the
time
between
the
rising
edge
of
RLCK
and
the
rising
edge
of
WCLK
is
less
than
t
SKEW1
,
then
the
IR
assertion
may
be
delayed
an
extra
WCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
for
PAF
to
go
HIGH
during
the
current
clock
cycle.
If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
tha
nt
SKEW2
,then
the
PAF
deassertion
time
may
be
delayed
an
extra
WCLK
cycle.
3.
LD
=
HIGH
4.
n=
PAE
offset,
m
=
PAF
offset,
D
=
maximum
FIFO
depth
=
257
words
for
the
IDT72805,
513
words
for
the
IDT72815,
1,025
words
for
the
IDT72825,
2,049
w
ords
for
IDT72835
and
4,097
words
for
IDT72845.
5.
Select
this
mode
by
setting
(
FL
,RXI
,WXI
)=
(1,0,1)
during
Reset.
WCLK
12
WEN
D
0
-
D
17
RCLK
tENS
REN
Q
0
-Q
17
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
tOHZ
tSKEW1
tENH
tDS
tDH
tOE
tA
tPAFS
tWFF
tENS
OE
tSKEW2
W
D
3139
drw
21
tPAES
W
[D-n]
W
[D-n-1]
tA
tHF
tREF
W
[D-1]
W
D
tA
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
1
tENS
D-1
]
[
W
D-1
]
[
W
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