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參數(shù)資料
| 型號： | IDT72825LB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
| 中文描述： | CMOS雙SyncFIFO雙256 × 18，雙512 × 18，雙1,024 × 18，雙2,048 × 18，雙4,096 × 18 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 334K |
| 代理商： | IDT72825LB |
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
4
Symbol
DA
0
–DA
17
DB
0
-DB
17
RSA
RSB
WCLKA
WCLKB
WENA
WENB
RCLKA
RCLKB
RENA
RENB
OEA
OEB
LDA
LDB
Name
I/O
I
Description
Data Inputs
Data inputs for an 18-bit bus.
Reset
I
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAMarray,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an initial WRITE after power-up.
When
WEN
is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
Write Clock
I
Write Enable
I
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When
WEN
is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the
FF
is LOW.
When
REN
is LOW, data is read fromthe FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
Read Clock
I
Read Enable
I
When
REN
is LOW, data is read fromthe FIFO on every LOW-to-HIGH transition of RCLK. When
REN
is HIGH,
the output register holds the previous data. Data will not be read fromthe FIFO if the
EF
is LOW.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a high-impedance
state.
When
LD
is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when
WEN
is LOW. When
LD
is LOW, data on the outputs Q0–Q11 is read fromthe
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when
REN
is LOW.
In the single device or width expansion configuration,
FL
together with
WXI
and
RXI
determne if the mode is
IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the
PAE
/
PAF
flags are
synchronous or asynchronous. (See Table I.) In the Daisy Chain Depth Expansion configuration,
FL
is grounded
on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
In the single device or width expansion configuration,
WXI
together with
FL
and
RXI
determne if the mode is
IDT Standard mode or FWFT mode, as well as whether the
PAE
/
PAF
flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
WXI
is connected to
WXO
(Write Expansion
Out) of the previous device.
In the single device or width expansion configuration,
RXI
together with
FL
and
WXI
, determne if the mode is
IDT Standard mode or FWFT mode, as well as whether the
PAE
/
PAF
flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
RXI
is connected to
RXO
(Read Expansion
Out) of the previous device.
In the IDT Standard mode, the
FF
function is selected
FF
indicates whether or not the FIFO memory is full. In
the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for writing to
the FIFO memory.
In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO memory is empty.
In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available at the
outputs.
When
PAE
is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is 31 fromempty for IDT72805LB, 63 fromempty for IDT72815LB, and 127 fromempty for
IDT72825LB/72835LB/72845LB.
When
PAF
is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is 31 fromfull for IDT72805LB, 63 fromfull for IDT72815LB, and 127 fromfull for IDT72825LB/72835LB/
72845LB.
In the single device or width expansion configuration, the device is more than half full when
HF
is LOW. In the
depth expansion configuration, a pulse is sent from
WXO
to
WXI
of the next device when the last location in
the FIFO is written.
In the depth expansion configuration, a pulse is sent from
RXO
to
RXI
of the next device when the last location
in the FIFO is read.
Data outputs for an 18-bit bus.
Output Enable
I
Load
I
FLA
FLB
First Load
I
WXIA
WXIB
Write Expansion
Input
I
RXIA
RXIB
Read Expansion
Input
I
FFA
/
IRA
FFB
/
IRB
Full Flag/
Input Ready
O
EFA
/
ORA
EFB
/
ORB
Empty Flag/
Output Ready
O
PAEA
PAEB
Programmable
Almost-Empty flag
O
PAFA
PAFB
Programmable
Almost-Full flag
O
WXOA
/
HFA
WXOB
/
HFB
Write Expansion
Out/Half-Full Flag
O
RXOA
RXOB
QA
0
–QA
17
QB
0
-QB
17
V
CC
GND
Read Expansion
Out
Data Outputs
O
O
Power
Ground
+5V power supply pins.
Ground pins.
PIN DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| IDT72825LB10PF | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
| IDT72825LB10PFI | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
| IDT72825LB15BG | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
| IDT72825LB15BGI | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
| IDT72825LB15PF | CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72825LB10PF | 功能描述:IC FIFO SYNC DL 1024X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72825LB10PF8 | 功能描述:IC FIFO SYNC DL 1024X18 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72825LB10PFG | 功能描述:IC FIFO 1024X18 SYNC DL 128TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72825LB10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC DL 1024X18 128TQFP |
| IDT72825LB15BG | 功能描述:IC FIFO SYNC DL 1024X18 121BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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