參數(shù)資料
型號(hào): IDT72825LB25BG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
中文描述: 1K X 18 BI-DIRECTIONAL FIFO, 15 ns, PBGA121
封裝: 16 X 16 MM, PLASTIC, BGA-121
文件頁數(shù): 9/26頁
文件大?。?/td> 334K
代理商: IDT72825LB25BG
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
NOTES:
1. In a daisy-chain depth expansion,
FL
is held LOW for the "first load device". The
RXI
and
WXI
inputs are driven by the corresponding
RXO
and
WXO
outputs of the preceding device.
2. In a daisy-chain depth expansion,
FL
is held HIGH for members of the expansion other than the "first load device". The
RXI
and
WXI
inputs are driven by the corresponding
RXO
and
WXO
outputs of the preceding device.
TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET
FL
RXI
WXI
EF
/
OR
FF
/
IR
PAE
,
PAF
FIFO TIMING MODE
0
0
0
Single register-buffered
Empty Flag
Triple register-buffered
Output Ready Flag
Double register-buffered
Empty Flag
Single register-buffered
Empty Flag
Single register-buffered
Empty Flag
Triple register-buffered
Output Ready Flag
Double register-buffered
Empty Flag
Single register-buffered
Empty Flag
Single register-buffered
Full Flag
Double register-buffered
Input Ready Flag
Double register-buffered
Full Flag
Single register-buffered
Full Flag
Single register-buffered
Full Flag
Double register-buffered
Input Ready Flag
Double register-buffered
Full Flag
Single register-buffered
Full Flag
Asynchronous
Standard
0
0
1
Asynchronous
FWFT
0
1
0
Asynchronous
Standard
0
(1)
1
1
Asynchronous
Standard
1
0
0
Synchronous
Standard
1
0
1
Synchronous
FWFT
1
1
0
Synchronous
Standard
1
(2)
1
1
Asynchronous
Standard
TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE
Empty Flag (
EF
)
Buffered Output
Full Flag (
FF
)
Buffered Output
Partial Flags
Timing Mode
Programming at Reset
FL
RXI
Flag Timing
Diagrams
WXI
Single
Single
Double
Double
Single
Single
Double
Double
Asynch
Sync
Asynch
Synch
0
1
0
1
0
0
1
1
0
0
0
0
Figure 9, 10
Figure 9, 10
Figure 24, 26
Figure 24, 26
TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE
Output Ready (
OR
)
Input Ready (
IR
)
Partial Flags
Programming at Reset
FL
RXI
Flag Timing
Diagrams
WXI
Triple
Triple
Double
Double
Asynch
Sync
0
1
0
0
1
1
Figure 27
Figure 20, 21
相關(guān)PDF資料
PDF描述
IDT72805LB10BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
IDT72815LB10BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
IDT72825LB10BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
IDT72835LB10BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
IDT72845LB10BG CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
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